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----------------------------------------------------------------
|                                                              |
|                                                              |
|                             RCA                              |
|                                                              |
|               1     88888      000      22222                |
|              11    8     8    0   0    2     2               |
|               1    8     8   0   0 0        2                |
|               1     88888    0  0  0     222                 |
|               1    8     8   0 0   0    2                    |
|               1    8     8    0   0    2                     |
|              111    88888      000     2222222               |
|                                                              |
|    CDP1802 COSMAC Microprocessor Instruction Set Summary     |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                    _________    _________                    |
|                  _|         \__/         |_                  |
|       --> CLOCK |_|1                   40|_| Vdd             |
|            ____  _|                      |_  ____            |
|        --> WAIT |_|2                   39|_| XTAL -->        |
|           _____  _|                      |_  ______          |
|       --> CLEAR |_|3                   38|_| DMA IN <--      |
|                  _|                      |_  _______         |
|           <-- Q |_|4                   37|_| DMA OUT <--     |
|                  _|                      |_  _________       |
|         <-- SC1 |_|5                   36|_| INTERRUPT <--   |
|                  _|                      |_  ___             |
|         <-- SC0 |_|6                   35|_| MWR <--         |
|             ___  _|                      |_                  |
|         <-- MRD |_|7                   34|_| TPA -->         |
|                  _|                      |_                  |
|      <--> BUS 7 |_|8                   33|_| TPB -->         |
|                  _|                      |_                  |
|      <--> BUS 6 |_|9                   32|_| MA7 -->         |
|                  _|                      |_                  |
|      <--> BUS 5 |_|10       1802       31|_| MA6 -->         |
|                  _|                      |_                  |
|      <--> BUS 4 |_|11                  30|_| MA5 -->         |
|                  _|                      |_                  |
|      <--> BUS 3 |_|12                  29|_| MA4 -->         |
|                  _|                      |_                  |
|      <--> BUS 2 |_|13                  28|_| MA3 -->         |
|                  _|                      |_                  |
|      <--> BUS 1 |_|14                  27|_| MA2 -->         |
|                  _|                      |_                  |
|      <--> BUS 0 |_|15                  26|_| MA1 -->         |
|                  _|                      |_                  |
|             Vcc |_|16                  25|_| MA0 -->         |
|                  _|                      |_  ___             |
|          <-- N2 |_|17                  24|_| EF1 <--         |
|                  _|                      |_  ___             |
|          <-- N1 |_|18                  23|_| EF2 <--         |
|                  _|                      |_  ___             |
|          <-- N0 |_|19                  22|_| EF3 <--         |
|                  _|                      |_  ___             |
|             Vss |_|20                  21|_| EF4 <--         |
|                   |______________________|                   |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|Written by     Jonathan Bowen                                 |
|               Programming Research Group                     |
|               Oxford University Computing Laboratory         |
|               8-11 Keble Road                                |
|               Oxford OX1 3QD                                 |
|               England                                        |
|                                                              |
|               Tel +44-865-273840                             |
|                                                              |
|Created        August 1981                                    |
|Updated        April 1985                                     |
|Issue          1.3                Copyright (C) J.P.Bowen 1985|
----------------------------------------------------------------
----------------------------------------------------------------
|Mnem. |Op|F|Description                 |Notes                |
|------+--+-+----------------------------+---------------------|
|ADC   |74|*|Add with Carry              |{DF,D}=mx+D+DF       |
|ADCI i|7C|*|Add with Carry Immediate    |{DF,D}=mp+D+DF,p=p+1 |
|ADD   |F4|*|Add                         |{DF,D}=mx+D          |
|ADI  i|FC|*|Add Immediate               |{DF,D}=mp+D,p=p+1    |
|AND   |F2|*|Logical AND                 |D={mx}&D             |
|ANI  i|FA|*|Logical AND Immediate       |D={mp}&D,p=p+1       |
|B1   a|34|-|Branch if EF1               |If EF1=1 BR else NBR |
|B2   a|35|-|Branch if EF2               |If EF2=1 BR else NBR |
|B3   a|36|-|Branch if EF3               |If EF3=1 BR else NBR |
|B4   a|37|-|Branch if EF4               |If EF4=1 BR else NBR |
|BDF  a|33|-|Branch if DF                |If DF=1 BR else NBR  |
|BGE  a|33|-|Branch if Greater or Equal  |See BDF              |
|BL   a|38|-|Branch if Less              |See BNF BR else NBR  |
|BM   a|38|-|Branch if Minus             |See BNF              |
|BN1  a|3C|-|Branch if Not EF1           |If EF1=0 BR else NBR |
|BN2  a|3D|-|Branch if Not EF2           |If EF2=0 BR else NBR |
|BN3  a|3E|-|Branch if Not EF3           |If EF3=0 BR else NBR |
|BN4  a|3F|-|Branch if Not EF4           |If EF4=0 BR else NBR |
|BNF  a|38|-|Branch if Not DF            |If DF=0 BR else NBR  |
|BNQ  a|39|-|Branch if Not Q             |If Q=0 BR else NBR   |
|BNZ  a|3A|-|Branch if D Not Zero        |If D=1 BR else NBR   |
|BPZ  a|33|-|Branch if Positive or Zero  |See BDF              |
|BQ   a|31|-|Branch if Q                 |If Q=1 BR else NBR   |
|BR   a|30|-|Branch                      |pl=mp                |
|BZ   a|32|-|Branch if D Zero            |If D=0 BR else NBR   |
|DEC  r|2N|-|Decrement register N        |n=n-1                |
|DIS   |71|-|Disable                     |{X,P}=mx,x=x+1,IE=0  |
|GHI  r|9N|-|Get High register N         |D=nh                 |
|GLO  r|8N|-|Get Low register N          |D=nl                 |
|IDL   |00|-|Idle (wait for DMA or int.) |Bus=m0               |
|INC  r|1N|-|Increment register N        |n=n+1                |
|INP  d|6N|-|Input (N=d+8=9-F)           |mx=Bus,D=Bus,Nlines=d|
|IRX   |60|-|Increment register X        |x=x+1                |
|LBDF a|C3|-|Long Branch if DF           |If DF=1 LBR else LNBR|
|LBNF a|C8|-|Long Branch if Not DF       |If DF=0 LBR else LNBR|
|LBNQ a|C9|-|Long Branch if Not Q        |If Q=0 LBR else LNBR |
|LBNZ a|CA|-|Long Branch if D Not Zero   |If D=1 LBR else LNBR |
|LBQ  a|C1|-|Long Branch if Q            |If Q=1 LBR else LNBR |
|LBR  a|C0|-|Long Branch                 |p=mp                 |
|LBZ  a|C2|-|Long Branch if D Zero       |If D=0 LBR else LNBR |
|LDA  r|4N|-|Load advance                |D=mn,n=n+1           |
|LDI  i|F8|-|Load Immediate              |D=mp,p=p+1           |
|LDN  r|0N|-|Load via N (except N=0)     |D=mn                 |
|LDX   |F0|-|Load via X                  |D=mx                 |
|LDXA  |72|-|Load via X and Advance      |D=mx,x=x+1           |
|LSDF  |CF|-|Long Skip if DF             |If DF=1 LSKP else NOP|
|LSIE  |CC|-|Long Skip if IE             |If IE=1 LSKP else NOP|
|LSKP  |C8|-|Long Skip                   |See NLBR             |
|LSNF  |C7|-|Long Skip if Not DF         |If DF=0 LSKP else NOP|
|LSNQ  |C5|-|Long Skip if Not Q          |If Q=0 LSKP else NOP |
|LSNZ  |C6|-|Long Skip if D Not Zero     |If D=1 LSKP else NOP |
|LSQ   |CD|-|Long Skip if Q              |If Q=1 LSKP else NOP |
|LSZ   |CE|-|Long Skip if D Zero         |If D=0 LSKP else NOP |
|MARK  |79|-|Push X,P to stack  (T={X,P})|m2={X,P},X=P,r2=r2-1 |
|NBR   |38|-|No short Branch (see SKP)   |p=p+1                |
|NLBR a|C8|-|No Long Branch (see LSKP)   |p=p+2                |
|NOP   |C4|-|No Operation                |Continue             |
|OR    |F1|*|Logical OR                  |D={mx}vD             |
|ORI  i|F9|*|Logical OR Immediate        |D={mp}vD,p=p+1       |
|OUT  d|6N|-|Output (N=d=1-7)            |Bus=mx,x=x+1,Nlines=d|
|PLO  r|AN|-|Put Low register N          |nl=D                 |
|PHI  r|BN|-|Put High register N         |nh=D                 |
|REQ   |7A|-|Reset Q                     |Q=0                  |
|RET   |70|-|Return                      |{X,P}=mx,x=x+1,IE=1  |
|RSHL  |7E|*|Ring Shift Left             |See SHLC             |
|RSHR  |76|*|Ring Shift Right            |See SHRC             |
|SAV   |78|-|Save                        |mx=T                 |
|SDB   |75|*|Subtract D with Borrow      |{DF,D}=mx-D-DF       |
|SDBI i|7D|*|Subtract D with Borrow Imm. |{DF,D}=mp-D-DF,p=p+1 |
|SD    |F5|*|Subtract D                  |{DF,D}=mx-D          |
|SDI  i|FD|*|Subtract D Immediate        |{DF,D}=mp-D,p=p+1    |
|SEP  r|DN|-|Set P                       |P=N                  |
|SEQ   |7B|-|Set Q                       |Q=1                  |
|SEX  r|EN|-|Set X                       |X=N                  |
|SHL   |FE|*|Shift Left                  |{DF,D}={DF,D,0}<-    |
|SHLC  |7E|*|Shift Left with Carry       |{DF,D}={DF,D}<-      |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnem. |Op|F|Description                 |Notes                |
|------+--+-+----------------------------+---------------------|
|SHR   |F6|*|Shift Right                 |{D,DF}=->{0,D,DF}    |
|SHRC  |76|*|Shift Right with Carry      |{D,DF}=->{D,DF}      |
|SKP   |38|-|Short Skip                  |See NBR              |
|SMB   |77|*|Subtract Memory with Borrow |{DF,D}=D-mx-{~DF}    |
|SMBI i|7F|*|Subtract Mem with Borrow Imm|{DF,D}=D-mp-~DF,p=p+1|
|SM    |F7|*|Subtract Memory             |{DF,D}=D-mx          |
|SMI  i|FF|*|Subtract Memory Immediate   |{DF,D}=D-mp,p=p+1    |
|STR  r|5N|-|Store via N                 |mn=D                 |
|STXD  |73|-|Store via X and Decrement   |mx=D,x=x-1           |
|XOR   |F3|*|Logical Exclusive OR        |D={mx}.D             |
|XRI  i|FB|*|Logical Exclusive OR Imm.   |D={mp}.D,p=p+1       |
|      |  |-|Interrupt action            |T={X,P},P=1,X=2,IE=0 |
|------+--+-+--------------------------------------------------|
|      |??| |8-bit hexadecimal opcode                          |
|      |?N| |Opcode with register/device in low 4/3 bits       |
|      |  |-|DF flag unaffected                                |
|      |  |*|DF flag affected                                  |
|-----------+--------------------------------------------------|
| mn        |Register addressing                               |
| mx        |Register-indirect addressing                      |
| mp        |Immediate addressing                              |
| R( )      |Stack addressing (implied addressing)             |
|-----------+--------------------------------------------------|
|DFB n(,n)  |Define Byte                                       |
|DFS n      |Define Storage block                              |
|DFW n(,n)  |Define Word                                       |
|-----------+--------------------------------------------------|
| D         |Data register (accumulator, 8-bit)                |
| DF        |Data Flag (ALU carry, 1-bit)                      |
| I         |High-order instruction digit (4-bit)              |
| IE        |Interrupt Enable (1-bit)                          |
| N         |Low-order instruction digit (4-bit)               |
| P         |Designates Program Counter register (4-bit)       |
| Q         |Output flip-flop (1-bit)                          |
| R         |1 of 16 scratchpad Registers(16-bit)              |
| T         |Holds old {X,P} after interrupt (X high, 8-bit)   |
| X         |Designates Data Pointer register (4-bit)          |
|-----------+--------------------------------------------------|
| mn        |Memory byte addressed by R(N)                     |
| mp        |Memory byte addressed by R(P)                     |
| mx        |Memory byte addressed by R(X)                     |
| m?        |Memory byte addressed by R(?)                     |
| n         |Short form for R(N)                               |
| nh        |High-order byte of R(N)                           |
| nl        |Low-order byte of R(N)                            |
| p         |Short form for R(P)                               |
| pl        |Low-order byte of R(P)                            |
| r?        |Short form for R(?)                               |
| x         |Short form for R(X)                               |
|-----------+--------------------------------------------------|
| R(N)      |Register specified by N                           |
| R(P)      |Current program counter                           |
| R(X)      |Current data pointer                              |
| R(?)      |Specific register                                 |
|-----------+--------------------------------------------------|
| a         |Address expression                                |
| d         |Device number (1-7)                               |
| i         |Immediate expression                              |
| n         |Expression                                        |
| r         |Register (hex digit or an R followed by hex digit)|
|-----------+--------------------------------------------------|
| +         |Arithmetic addition                               |
| -         |Arithmetic subtraction                            |
| *         |Arithmetic multiplication                         |
| /         |Arithmetic division                               |
| &         |Logical AND                                       |
| ~         |Logical NOT                                       |
| v         |Logical inclusive OR                              |
| .         |Logical exclusive OR                              |
| <-        |Rotate left                                       |
| ->        |Rotate right                                      |
| { }       |Combination of operands                           |
| ?         |Hexadecimal digit (0-F)                           |
| -->       |Input pin                                         |
| <--       |Output pin                                        |
| <-->      |Input/output pin                                  |
----------------------------------------------------------------


 


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