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----------------------------------------------------------------
|                                                              |
|                                                              |
|                            Intel                             |
|                                                              |
|             88888      000         4      88888              |
|            8     8    0   0       44     8     8             |
|            8     8   0   0 0     4 4     8     8             |
|             88888    0  0  0    4  4      88888              |
|            8     8   0 0   0   4444444   8     8             |
|            8     8    0   0        4     8     8             |
|             88888      000         4      88888              |
|                                                              |
|          8048/8049/8748/8749/8035/8039 Single-Chip           |
|            MICROCOMPUTER Instruction Set Summary             |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                    _________    _________                    |
|                  _|         \__/         |_                  |
|         <--> T0 |_|1                   40|_| Vcc (+5V)       |
|                  _|                      |_                  |
|       --> XTAL1 |_|2                   39|_| T1 <--          |
|                  _|                      |_                  |
|       --> XTAL2 |_|3                   38|_| P27 <-->        |
|           _____  _|                      |_                  |
|       --> RESET |_|4                   37|_| P26 <-->        |
|              __  _|                      |_                  |
|          --> SS |_|5                   36|_| P25 <-->        |
|             ___  _|                      |_                  |
|         --> INT |_|6                   35|_| P24 <-->        |
|                  _|                      |_                  |
|          --> EA |_|7                   34|_| P17 <-->        |
|              __  _|                      |_                  |
|          <-- RD |_|8                   33|_| P16 <-->        |
|            ____  _|                      |_                  |
|        <-- PSEN |_|9        8048       32|_| P15 <-->        |
|              __  _|         8049         |_                  |
|          <-- WR |_|10       8748       31|_| P14 <-->        |
|                  _|         8749         |_                  |
|         <-- ALE |_|11       8035       30|_| P13 <-->        |
|                  _|         8039         |_                  |
|        <--> DB0 |_|12                  29|_| P12 <-->        |
|                  _|                      |_                  |
|        <--> DB1 |_|13                  28|_| P11 <-->        |
|                  _|                      |_                  |
|        <--> DB2 |_|14                  27|_| P10 <-->        |
|                  _|                      |_                  |
|        <--> DB3 |_|15                  26|_| Vdd             |
|                  _|                      |_                  |
|        <--> DB4 |_|16                  25|_| PROG <-->       |
|                  _|                      |_                  |
|        <--> DB5 |_|17                  24|_| P23 <-->        |
|                  _|                      |_                  |
|        <--> DB6 |_|18                  23|_| P22 <-->        |
|                  _|                      |_                  |
|        <--> DB7 |_|19                  22|_| P21 <-->        |
|                  _|                      |_                  |
|       (GND) Vss |_|20                  21|_| P20 <-->        |
|                   |______________________|                   |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|                                                              |
|Written by     Jonathan Bowen                                 |
|               Programming Research Group                     |
|               Oxford University Computing Laboratory         |
|               8-11 Keble Road                                |
|               Oxford OX1 3QD                                 |
|               England                                        |
|                                                              |
|               Tel +44-865-273840                             |
|                                                              |
|Created        May 1983                                       |
|Updated        April 1985                                     |
|Issue          1.1                Copyright (C) J.P.Bowen 1985|
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic  |Op|CA|F|~|Description              |Notes          |
|----------+--+--+-+-+-------------------------+---------------|
|ADD  A,rr |68|**|A|1|Add register             |A=A+rr         |
|ADD  A,@r |60|**|B|1|Add memory               |A=A+[r]        |
|ADD  A,#n |03|**|C|2|Add immediate            |A=A+n          |
|ADDC A,rr |78|**|A|1|Add with Carry register  |A=A+rr+C       |
|ADDC A,@r |70|**|B|1|Add with Carry memory    |A=A+[r]+C      |
|ADDC A,#n |13|**|C|2|Add with Carry immediate |A=A+n+C        |
|ANL  A,rr |58|--|A|1|AND Logical register     |A=A&rr         |
|ANL  A,@r |50|--|B|1|AND Logical memory       |A=A&[r]        |
|ANL  A,#n |53|--|C|2|AND Logical Immediate    |A=A&n          |
|ANL  pp,#n|98|--|D|2|AND Logical I/O port     |pp=pp&n        |
|ANLD ep,A |9C|--|E|2|AND Logical expander port|ep=ep&A        |
|CALL a    |14|--|F|2|Call subroutine          |[SP]+={PSW,PC},|
|CLR  A    |27|--|G|1|Clear accumulator        |A=0        PC=a|
|CLR  C    |97|0-|G|1|Clear carry status       |C=0            |
|CLR  F0   |85|--|G|1|Clear flag #0            |F0=0           |
|CLR  F1   |A5|--|G|1|Clear flag #1            |F1=0           |
|CPL  A    |37|--|G|1|Complement accumulator   |A=~A           |
|CPL  C    |A7|*-|G|1|Complement carry status  |C=~C           |
|CPL  F0   |95|--|G|1|Complement flag #0       |F0=~F0         |
|CPL  F1   |B5|--|G|1|Complement flag #1       |F1=~F1         |
|DA   A    |57|--|G|1|Decimal Adjust acc.      |A=BCD{A}       |
|DEC  A    |07|--|G|1|Decrement accumulator    |A=A-1          |
|DEC  rr   |C8|--|A|1|Decrement register       |rr=rr-1        |
|DIS  I    |15|--|G|1|Disable external int.    |               |
|DIS  TCNTI|35|--|G|1|Disable timer interrupt  |               |
|DJNZ rr,l |E8|--|H|2|Dec. and Jump if Non-Zero|rr=rr-1,if rr  |
|EN   I    |05|--|G|1|Enable external interrupt|               |
|EN   TCNTI|25|--|G|1|Enable timer interrupt   |               |
|ENT0 CLK  |75|--|G|1|Enable timer output      |               |
|IN   A,p  |08|--|I|2|Input from I/O port      |A=p            |
|INC  A    |17|--|G|1|Increment accumulator    |A=A+1          |
|INC  rr   |18|--|A|1|Increment register       |rr=rr+1        |
|INC  @r   |10|--|B|1|Increment memory         |[r]=[r]+1      |
|INS  A,BUS|08|--|G|2|Input bus with strobe    |A=BUS          |
|JBn  l    |12|--|J|2|Jump if Bit set (n=0-7)  |If A<n>=1      |
|JC   l    |F6|--|K|2|Jump if Carry set        |If C=1         |
|JF0  l    |B6|--|K|2|Jump if Flag #0 set      |If F0=1        |
|JF1  l    |76|--|K|2|Jump if Flag #1 set      |If F1=1        |
|JMP  a    |04|--|F|2|Unconditional Jump       |PC=a           |
|JMPP @A   |B3|--|G|2|Jump on accumulator      |PC=PC<8:11>+A  |
|JNC  l    |E6|--|K|2|Jump if Not Carry        |If C=0         |
|JNI  l    |86|--|K|2|Jump if Not Interrupt    |If I=0         |
|JNT0 l    |26|--|K|2|Jump if Not Test i/p #0  |If T0=0        |
|JNT1 l    |46|--|K|2|Jump if Not Test i/p #1  |If T1=0        |
|JNZ  l    |96|--|K|2|Jump if Not Zero         |If A<>0        |
|JOBF l    |86|--|K|2|Jump if OBF set          |If OBF=1       |
|JTF  l    |16|--|K|2|Jump if Timer Flag set   |If TF=1, TF=0  |
|JT0  l    |36|--|K|2|Jump if Test i/p #0 set  |If T0=1        |
|JT1  l    |56|--|K|2|Jump if Test i/p #1 set  |If T1=1        |
|JZ   l    |C6|--|K|2|Jump if Zero             |If A=0         |
|MOV  A,#n |23|--|C|2|Move from immediate      |A=n            |
|MOV  A,PSW|C7|--|G|1|Move from PSW            |A=PSW          |
|MOV  A,rr |F8|--|A|1|Move from register       |A=rr           |
|MOV  A,@r |F0|--|B|1|Move from memory         |A=[r]          |
|MOV  A,T  |42|--|G|1|Move from timer          |A=T            |
|MOV  PSW,A|D7|**|G|1|Move to PSW              |PSW=A          |
|MOV  rr,A |A8|--|A|1|Move to register         |rr=A           |
|MOV  rr,#n|B8|--|L|2|Move immediate to reg.   |rr=n           |
|MOV  @r,A |A0|--|B|1|Move to memory           |[r]=A          |
|MOV  @r,#n|B0|--|M|2|Move immediate to memory |[r]=n          |
|MOV  T,A  |62|--|G|1|Move to timer            |T=A            |
|MOVD A,ep |0C|--|E|2|Move from expander port  |A=ep           |
|MOVD ep,A |3C|--|E|2|Move to expander port    |ep=A           |
|MOVP A,@A |A3|--|G|1|2|Move from memory       |A=[PC<8:11>+A] |
|MOVP3 A,@A|E3|--|G|2|Move from memory         |A=[300H+A]     |
|MOVX A,@r |80|--|B|2|Move from external memory|A=[r]          |
|MOVX @r,A |90|--|B|2|Move to external memory  |[r]=A          |
|NOP       |00|--|G|1|No Operation             |               |
|ORL  A,rr |48|--|A|1|OR Logical register      |A=Avrr         |
|ORL  A,@r |40|--|B|1|OR Logical memory        |A=Av[r]        |
|ORL  A,#n |43|--|C|2|OR Logical immediate     |A=Avn          |
|ORL  pp,#n|88|--|D|2|OR Logical I/O port      |pp=ppvn        |
|ORLD ep,A |8C|--|E|2|OR Logical expander port |ep=epvA        |
|OUTL BUS,A|02|--|G|2|Output to bus            |BUS=A          |
|OUTL p,A  |38|--|I|2|Output to I/O port       |p=A            |
|RET       |83|--|G|2|Return from subroutine   |PC=[SP]-       |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic  |Op|CA|F|~|Description              |Notes          |
|----------+--+--+-+-+-------------------------+---------------|
|RETR      |93|**|G|2|Return and Restore status|{PC,PSW}=[SP]- |
|RL   A    |E7|--|G|1|Rotate Left              |A={A}<-        |
|RLC  A    |F7|*-|G|1|Rotate Left thru Carry   |A={A,C}<-      |
|RR   A    |77|--|G|1|Rotate Right             |A=->{A}        |
|RRC  A    |67|*-|G|1|Rotate Right thru Carry  |A=->{C,A}      |
|SEL  MBk  |E5|--|N|1|Select Memory Bank       |PC<11>=k       |
|SEL  RBk  |C5|--|N|1|Select Register Bank     |Reg bank=k     |
|STOP TCNT |65|--|G|1|Stop timer/counter       |               |
|STRT CNT  |45|--|G|1|Start counter            |               |
|STRT T    |55|--|G|1|Start timer              |               |
|SWAP A    |47|--|G|1|Swap accumulator nibbles |A<0:3><->A<4:7>|
|XCH  A,rr |28|--|A|1|Exchange register        |A<->rr         |
|XCH  A,@r |20|--|B|1|Exchange memory          |A<->[r]        |
|XCHD A,@r |30|--|B|1|Exchange lower nibbles   |A<0:3><->[r<:>]|
|XRL  A,rr |D8|--|A|1|Exclusive OR register    |A=Axrr         |
|XRL  A,@r |D0|--|B|1|Exclusive OR memory      |A=Ax[r]        |
|XRL  A,#n |D3|--|C|2|Exclusive OR immediate   |A=Axn          |
|-------------+--+-+-+-----------------------------------------|
| PSW         |-*| | |Flag unaffected/affected or zero (0)     |
| C           |C | | |Carry (Bit 7)                            |
| AC          | A| | |Auxilary Carry (Bit 6)                   |
| F0   F1     |  | | |Flags (F0, bit 5, F1 bit 4)              |
| SP          |  | | |Stack Pointer (Bits 0-2)                 |
|----------------+-+-+-----------------------------------------|
| -----nnn       |A| |nnn = R0/R1/R2/R3/R4/R5/R6/R7 (3 bits)   |
| -------r       |B| |r   = R0/R1 (1 bit)                      |
| -------- MM    |C| |MM  = 8 bits of immediate data           |
| ------pp MM    |D| |pp  = BUS/P1/P2/? (2 bits)               |
| ------ee       |E| |ee  = P4/P5/P6/P7 (2 bits)               |
| xxx----- XX    |F| |xxx = high-order 3 bits of memory address|
| --------       |G| |XX  = low-order 8 bits of memory address |
| -----nnn XX    |H| |nnn = as above                           |
| ------qq       |I| |qq  = ?/P1/P2/? (2 bits)                 |
| bbb----- XX    |J| |bbb = 3-bit bit number of accumulator    |
| -------- XX    |K| |XX  = as above                           |
| -----nnn MM    |L| |nnn = as above                           |
| -------r MM    |M| |r   = as above                           |
| ---k----       |N| |k   = 0/1 (1 bit)                        |
|--------------------+-----------------------------------------|
| A                  |Accumulator (8-bit)                      |
| BUS                |Bus I/O port (8-bit)                     |
| OBF                |Output Buffer Full flag (1-bit)          |
| MB0  MB1           |Memory Banks                             |
| P1   P2            |I/O Ports (8-bit)                        |
| PC                 |Program Counter register (12-bit)        |
| PORT               |I/O Port P1 and P2                       |
| PSW                |Processor Status Word (8-bit)            |
| RB0  RB1           |Register Banks                           |
| Rn                 |Registers (8-bit, n=0-7)                 |
| Rn'                |Alternative Registers (8-bit, n=0-7)     |
| T0   T1            |Test inputs                              |
|--------------------+-----------------------------------------|
| a                  |11-bit address quantity (0 to 2047)      |
| ep                 |8243 expander port P4, P5, P6 or P7      |
| k                  |1-bit data quantity (0 or 1)             |
| l                  |Low-order 8 bits of a memory address     |
| n                  |8-bit data quantity (0 to 255)           |
| p                  |I/O port P1 or P2                        |
| pp                 |I/O port PORT, P1 or P2                  |
| r                  |Register R0 or R1                        |
| rr                 |Register R0, R1, R2, R3, R4, R5, R6 or R7|
|--------------------+-----------------------------------------|
| +    -             |Arithmetic addition/subtraction          |
| &    ~             |Logical AND/NOT                          |
| v    x             |Logical inclusive/exclusive OR           |
| <-   ->            |Rotate left/right                        |
| <->                |Exchange                                 |
| < >  < : >         |Bit number/range                         |
| [ ]                |Indirect addressing                      |
| [ ]+ -[ ]          |Indirect address auto-increment/decrement|
| { }                |Combination of operands                  |
|--------------------+-----------------------------------------|
| 00H to 07H         |General purpose registers R0-R7 (8-bit)  |
| 08H to 17H         |Stack area S0-S7 (16-bit)                |
| 18H to 1FH         |Alternative registers R0'-R7' (8-bit)    |
| 20H to 3FH         |General scratchpad memory area           |
----------------------------------------------------------------


 


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