MikesArcade.com Coin-op Video Arcade Technical Information Archive
  Home  |  Repair Logs  |  Game Manuals  |  Monitor Manuals  |  Online Store  |  Links  |  Contact Us
Technical Info
  Repair Logs
  Pacman fixes
  Manuals & Schematics
  Monitor Manuals
  Nintendo Game List
  Nintendo Joysticks
  Nintendo Buttons
  Data I/O Promlink 6.10
Spies Wiretap Archives
  Coin-op Video Game List
  Game Conversions
  The Mixed Bag
  PCB Pinouts and DIPs
PDF Game Artwork
  Coin door inserts, etc.
  Instructions cards
  Operation Sheets
  Control Panel & Bezels
Jukebox
  Title Strip Creator
Tutorials
  Component markings...
  Crating a game
  Build your own cabinet
Board Upgrades
  Double Donkey Kong
Wanted
  Items I'm looking for
Miscellaneous
  Links
  Contact Us
Certifications
  Valid HTML 4.01!
 
Timing information for ICs is not yet available, and only TTL, 4000-series
CMOS and some microprocessor (support) chips are included.  For now, it is
not clear how the format used can be extended to include linear ICs, as these
usually require much more additional information such as a block diagram.

The current file uses the PC8 character set (a.k.a. codepage 437), but can
be converted to 7-bit ASCII without too much trouble (losing some niceties).
As it is, it is small and simple enough to keep it in your notebook PC for
when you are out in the field, it even fits in a HP100LX palmtop PC.
It might be possible to create a mail-server so that it may be accessed by
novice users of sci.electronics.  For now, I am unable to run a mail-server
on my login account, but perhaps someone will volunteer.

To minimize the amount of information needed per IC, a structured format
is used in the descriptions, and only features that differ from the
assumptions below are indicated.  Truth tables are not yet available for
all ICs, simply because creating them takes a long time.
The layout of the file is dictated by the fortune-cookie program I use to
sort this file (alphabetically -- not by number).

Anyone wanting to add this information should feel free to do so, but
please to not post changed versions.  Instead, mail additions to
falstaff@xs4all.nl.

Frank



PIN IDENTIFICATION
==================

General:
 * Missing pins have no pin number.
 * Unconnected pins and test pins that should be left floating have no
   identification.
 * Clock signals are identified by CLK for positive-edge triggering or /CLK
   for negative-edge triggering.
 * Reset (clear) inputs are identified by RST.
 * Set inputs are identified by SET.
 * For 3-state devices, output enables are indicated by OE.
 * When a pin has two modes, or selects between two operations, then the
   two may be separated by a slash.  An inversion slash may still be present
   as in SH//LD for shift or load select.
 * Pins that have more than one function (selected by programming or the state
   of another pin) are indicated by both functions separated by a space.

Power supply:
 * The main power supply is indicated by VCC.
 * System ground is indicated by GND.
 * A secondary positive power supply may be indicated by VDD.
 * A negative power supply is indicated by VEE.
 * Programming power supply (usually higher than VCC) is indicated by VPP.

Gates, line drivers etc.:
 * Inputs are identified by letters starting from A.
 * Outputs are indicated by Y.

Flip-flops:
 * Inputs are identified by J and K, or D.
 * Outputs are indicated by Q.

Counters:
 * Load inputs are indicated by P followed by the counter stage number.
 * Outputs are indicated by Q followed by the counter stage number.
   Thus (assuming a binary counter) Q0 is the /2 output, Q1 the /4 output.

Shift registers:
 * Parallel inputs or bidirectional parallel I/O pins are identified by P
   followed by the shifter stage number. The rightmost stage in a shift
   register is number 0.
 * Serial inputs are identified by letters starting from D (for right shift)
   or from L (for left shift).  If more than one of either is available,
   the letter is followed by the shifter stage number it feeds.
 * Serial outputs are identified by Q, which may be followed by the shifter
   stage number if more than one serial output exists.
 * Parallel outputs are identified by Q (only if no serial outputs exist),
   Y (3-state outputs or output latch) or R (otherwise) followed by the
   shifter stage number.
 * Unidirectional shift registers shift to the right (towards stage 0).

Multiplexers:
 * Inputs are identified by A followed by a number.
 * Outputs are indicated by Y.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which case only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which input is selected.

Demultiplexers:
 * Inputs are indicated by A, preceded by a section number if more than one.
 * Outputs are identified by Y followed by a number.  When there is more than
   one multiplexer section, inputs are prefixed by a number indicating to
   which section they belong.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which output is selected.  For noninverting demultiplexers unselected
   outputs are 0, for inverting demultiplexers they are 1.

Analog multiplexers/demultiplexers:
 * Analog switches generally are bidirectional, and inputs and outputs can
   therefore be reversed.
   One side of the switch is indicated by X (optionally followed by a number),
   the other side is indicated by Y.
 * Select inputs are identified by S followed by a number starting at 0,
   unless there is only one select input in which only S is specified.
   When the S inputs are taken as a binary number, the value indicates
   which switch is selected.

Memories:
 * Address inputs are indicated by A followed by the bit number, starting
   from 0.  Multiport memories use RA or WA for separate read and write
   addresses, or A prefixed by the port number followed by the bit number.
 * Data inputs or data I/O are indicated by D followed by a number starting
   from 0.
 * Data outputs are indicated by Q followed by a number.

Oscillators:
 * One-inverter oscillators are indicated by X0 and X1 pins, where X0 is
   the inverters' output and X1 is the input.  If I happen not to know which
   is which, the pins are indicated by X1 and X2.  A crystal oscillator
   usually requires a crystal parallel to a 10M resistor, with two small
   capacitors to ground; but sometimes only a crystal is needed -- most
   often when a 32kHz watch crystal can be used.
 * Two-inverter oscillators are indicated by X1 (input), X0 (middle node)
   and X2 (output).  A crystal oscillator can then be made using X0 and X1.

Sections:
 * When a device has several (largely) independent sections, I/O pins
   are prefixed by the section number, starting from 1, as in 1J or /1Q.
 * Multi-bit functions, such as counters or 3-state buffers have I/O pins
   suffixed by the bit number, usually starting from 0 (except sometimes
   for counters which may have some outputs missing).
 * The section/bit numbering is used in a different way for (de)multiplexers.



TRUTH TABLES
============

For inputs, the following notations are used:
   0  : logic low level
   1  : logic high level
   X  : don't care, either 0 or 1
   /  : rising or positive-edge clock input
   \  : falling or negative-edge clock input
   !/ : not a rising edge, either 0, 1 or \
   !\ : not a falling edge, either 0, 1 or /
   .  : 'continued', used in compressing the table

For outputs, the following notations are used:
   0 : logic low level
   1 : logic high level
   Z : high impedance, either 3-state or open-collector not driving output
   - : no change (latched in closed state, or register value not changed)
   ? : undefined (although some manufacturers may define a behaviour)
   . : 'continued', used in compressing the table



ASSUMPTIONS FOR TTL DEVICES
===========================

Single/Dual Flip-flops:
 * The clock is positive-edge triggered.
 * Complementary outputs are available.

Multiple flip-flops:
 * Only inverting or noninverting outputs are available.

Synchronous counters:
 * The clock is positive-edge triggered.
 * LOAD,SET and RESET are synchronous.

Asynchronous counters:
 * The clock is negative-edge triggered.
 * LOAD,SET and RESET are asynchronous.

Shift registers:
 * The clock is positive-edge triggered.
 * LOAD and RESET (if available) are synchronous.


------------------------------------------------------------------------------
#
1458
Dual 741-type operational amplifiers.

     Ŀ
1OUT 1    8 VCC
-1In 2        7 2OUT
+1In 3  1458  6 -2In
 VEE 4        5 +2In
     
#
1488, 75188
TTL to RS232 level shifter.
The outputs are at RS-232 levels, and sometimes are connected to ground
through a small capacitor (up to 470 pF) to reduce slew-rate.
Note that 1B is missing (and can be taken to be 1 at all times).
Usually VDD=+12 and VEE=-12.

    Ŀ          Ŀ
VEE 1   14 VDD       A  B   Y  
 1A 2       13 4A       ͵
 1Y 3       12 4B        0  0  VDD 
 2A 4  1488 11 4Y        0  1  VDD 
 2B 5       10 3A        1  0  VDD 
 2Y 6        9 3B        1  1  VEE 
GND 7        8 3Y       
    
#
1489, 75189
RS232 to TTL level shifter.
A inputs are RS232-level inputs, C inputs are response control, a TTL
signal which could be used to adjust threshhold and hysteresis but is
generally unnecessary and unused. It is often tied through a 300 - 470 pF
capacitor to ground.

    Ŀ
 1A 1   14 VCC
 1C 2       13 4A
 1Y 3       12 4C
 2A 4  1489 11 4Y
 2C 5       10 3A
 2Y 6        9 3C
GND 7        8 3Y
    
#
16550
Asynchronous serial interface controller with DMA support and 16-byte FIFOs.

        Ŀ
     D0 1       40 VCC
     D1 2           39 /RI
     D2 3           38 /DCD
     D3 4           37 /DSR
     D4 5           36 /CTS
     D5 6           35 MR
     D6 7           34 /OUT1
     D7 8           33 /DTR
   RCLK 9           32 /RTS
    SIN 10  16550   31 /OUT2
   SOUT 11          30 INTR
    CS0 12          29 /RXRDY
    CS1 13          28 A0
   /CS2 14          27 A1
/CLKOUT 15          26 A2
     X1 16          25 /ADS
     X0 17          24 /TXRDY
    /WR 18          23 DDIS
     WR 19          22 RD
    GND 20          21 /RD
        
#
2401
IC 128x8 EEPROM with write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 WP
 A2 3  2401  6 SCL
GND 4        5 SDA
    
#
2402
IC 256x8 EEPROM with write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 WP
 A2 3  2402  6 SCL
GND 4        5 SDA
    
#
2404
IC 2x256x8 EEPROM with write protect.
Address is 1010xxy where x can be specified by the A1-2 inputs,
and y selects the 256-byte bank to use.
A0 has no function, but must be connected to GND or VCC.

    Ŀ
 A0 1    8 VCC
 A1 2        7 WP
 A2 3  2404  6 SCL
GND 4        5 SDA
    
#
2408
IC 4x256x8 EEPROM with write protect.
Address is 1010xyy where x can be specified by the A2 input,
and yy selects the 256-byte bank to use.
A0-1 have no function, but must be connected to GND or VCC.

    Ŀ
 A0 1    8 VCC
 A1 2        7 WP
 A2 3  2408  6 SCL
GND 4        5 SDA
    
#
2416
IC 8x256x8 EEPROM with write protect.
Address is 1010yyy where yyy selects the 256-byte bank to use.
A0-2 have no function, but must be connected to GND or VCC.

    Ŀ
 A0 1    8 VCC
 A1 2        7 WP
 A2 3  2416  6 SCL
GND 4        5 SDA
    
#
2465
IC 8kx8 EEPROM with programmable block write protect.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 GND
 A2 3  2465  6 SCL
GND 4        5 SDA
    
#
271001
128kx8 EPROM.

    Ŀ
VPP 1       32 VCC
A16 2           31 /PGM
A15 3           30
A12 4           29 A14
 A7 5           28 A13
 A6 6           27 A8
 A5 7           26 A9
 A4 8   271001  25 A11
 A3 9           24 /OE
 A2 10          23 A10
 A1 11          22 /CE
 A0 12          21 D7
 D0 13          20 D6
 D1 14          19 D5
 D2 15          18 D4
GND 16          17 D3
    
#
271024
64kx16 EPROM.

    Ŀ
VPP 1       40 VCC
/CE 2           39 /PGM
D15 3           38
D14 4           37 A15
D13 5           36 A14
D12 6           35 A13
D11 7           34 A12
D10 8           33 A11
 D9 9           32 A10
 D8 10  271024  31 A9
GND 11          30 GND
 D7 12          29 A8
 D6 13          28 A7
 D5 14          27 A6
 D4 15          26 A5
 D3 16          25 A4
 D2 17          24 A3
 D1 18          23 A2
 D0 19          22 A1
/OE 20          21 A0
    
#
27128
16kx8 EPROM.
Available in 300 and 600 mil packages.

    Ŀ
VPP 1       28 VCC
A12 2           27 /PGM
 A7 3           26 A13
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7   27128   22 /OE
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
272001
256kx8 EPROM.

    Ŀ
VPP 1       32 VCC
A16 2           31 /PGM
A15 3           30 A17
A12 4           29 A14
 A7 5           28 A13
 A6 6           27 A8
 A5 7           26 A9
 A4 8   272001  25 A11
 A3 9           24 /OE
 A2 10          23 A10
 A1 11          22 /CE
 A0 12          21 D7
 D0 13          20 D6
 D1 14          19 D5
 D2 15          18 D4
GND 16          17 D3
    
#
27256
32kx8 EPROM.
Available in 300 and 600 mil packages.

    Ŀ
VPP 1       28 VCC
A12 2           27 A14
 A7 3           26 A13
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7   27256   22 /OE
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
2732
4kx8 EPROM.

    Ŀ
 A7 1       24 VCC
 A6 2           23 A8
 A5 3           22 A9
 A4 4           21 A11
 A3 5           20 /OE VPP
 A2 6    2732   19 A10
 A1 7           18 /CE
 A0 8           17 D7
 D0 9           16 D6
 D1 10          15 D5
 D2 11          14 D4
GND 12          13 D3
    
#
274001
512kx8 EPROM.

    Ŀ
VPP 1       32 VCC
A16 2           31 A18
A15 3           30 A17
A12 4           29 A14
 A7 5           28 A13
 A6 6           27 A8
 A5 7           26 A9
 A4 8   274001  25 A11
 A3 9           24 /OE
 A2 10          23 A10
 A1 11          22 /CE
 A0 12          21 D7
 D0 13          20 D6
 D1 14          19 D5
 D2 15          18 D4
GND 16          17 D3
    
#
27512
64kx8 EPROM.
Available in 300 and 600 mil packages.

    Ŀ
A15 1       28 VCC
A12 2           27 A14
 A7 3           26 A13
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7   27512   22 /OE VPP
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
2764
8kx8 EPROM.
Available in 300 and 600 mil packages.

    Ŀ
VPP 1       28 VCC
A12 2           27 /PGM
 A7 3           26
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7    2764   22 /OE
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
2864
8kx8 EEPROM.

    Ŀ
    1       28 VCC
A12 2           27 /WE
 A7 3           26
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7    2864   22 /OE
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
4000
Dual 3-input NOR gates and inverter.

    Ŀ                ________
    1   14 VCC        /1Y=1A+1B+1C
    2       13 3C
 1A 3       12 3B             __
 1B 4  4000 11 3A         /2Y=2A
 1C 5       10 /3Y
/1Y 6        9 /2Y            ________
GND 7        8 2A         /3Y=3A+3B+3C
    
#
4001
Quad 2-input NOR gates.

    Ŀ             Ŀ           ___
 1A 1   14 VCC          A  B /Y       /Y = A+B
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
/2Y 4  4001 11 /4Y          0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
4002, 744002
Dual 4-input NOR gates.

    Ŀ             Ŀ       _________
/1Y 1   14 VCC          A  B  C  D /Y   /Y = (A+B+C+D)
 1A 2       13 /2Y         ͵
 1B 3       12 2D           0  0  0  0  1 
 1C 4  4002 11 2C           0  0  0  1  0 
 1D 5       10 2B           0  0  1  X  0 
    6        9 2A           0  1  X  X  0 
GND 7        8              1  X  X  X  0 
                 
#
4006
Dual 4-bit and dual 5-bit serial-in serial-out shift registers.

     Ŀ
 1D5 1   14 VCC
/1Q4 2       13 1Q1
 CLK 3       12 2Q0
 2D4 4  4006 11 2Q0
 3D4 5       10 3Q0
 4D5 6        9 4Q0
 GND 7        8 4Q1
     
#
4007
Dual complementary CMOS pair and unbuffered inverter.
For use as simple inverters, connect 1pS=3pS=VCC, 1nS=3nS=GND, 1pD=1nD=/1Y
and 2pD=2nD=/2Y.

     Ŀ
 1pD 1   14 VCC
 1pS 2       13 2pD
  1G 3       12 /3Y
 1nS 4  4007 11 3pS
 1nD 5       10 3G
  2G 6        9 3nS
 GND 7        8 2nD
     
#
4008
4-bit binary full adder with fast carry.

    Ŀ
 A3 1   16 VCC         =A+B+CIN
 B2 2       15 B3
 A2 3       14 CO
 B1 4       13 3
 A1 5  4008 12 2
 B0 6       11 1
 A0 7       10 0
GND 8        9 CI
    
#
4009
Hex inverters with level shifted outputs.
VDD may not be lower than VCC.

    Ŀ             Ŀ               _
VCC 1   16 VDD          A /Y           /Y = A
/Y1 2       15 /Y6         ͵
 A1 3       14 A6           0  1 
/Y2 4       13              1  0 
 A2 5  4009 12 /Y5         
/Y3 6       11 A5
 A3 7       10 /Y4
GND 8        9 A4
    
#
4010
Hex buffers with level shifted outputs.
VDD may not be lower than VCC.

    Ŀ             Ŀ
VCC 1   16 VDD          A  Y            Y = A
 Y1 2       15 Y6          ͵
 A1 3       14 A6           0  0 
 Y2 4       13              1  1 
 A2 5  4010 12 Y5          
 Y3 6       11 A5
 A3 7       10 Y4
GND 8        9 A4
    
#
40100
32-bit 3-state bidirectional serial-in serial-out shift register with separate
shift left and shift right serial in/outputs and both active high and active
low clocks.

      Ŀ
      1   16 VCC
/CLK2 2       15
 CLK1 3       14
  Q31 4       13 L//R
      5 40100 12 Q0
    L 6       11 D
      7       10
  GND 8        9 /LOOP
      
#
40101
9-bit odd/even parity generator/checker.

    Ŀ
 A0 1   14 VCC
 A1 2       13 A8
 A2 3       12 A7
 A3 4 40101 11 A6
 A4 5       10 A5
ODD 6        9 EVEN
GND 7        8 /EN
    
#
40102, 7440102
8-bit (2-digit) synchronous decade down counter with synchronous and
asynchronous load and reset.  Counter outputs only internally connected but
ripple carry and zero detect outputs available.

       Ŀ
   CLK 1   16 VCC
  /RST 2       15 /SLD
/CLKEN 3       14 /RCO
    P0 4       13 P7
    P1 5 40102 12 P6
    P2 6       11 P5
    P3 7       10 P4
   GND 8        9 /ALD
       
#
40103, 7440103
8-bit synchronous binary down counter with synchronous and asynchronous load
and reset.  Counter outputs only internally connected but ripple carry and
zero detect outputs available.

       Ŀ
   CLK 1   16 VCC
  /RST 2       15 /SLD
/CLKEN 3       14 /RCO
    P0 4       13 P7
    P1 5 40103 12 P6
    P2 6       11 P5
    P3 7       10 P4
   GND 8        9 /ALD
       
#
40104
4-bit 3-state bidirectional shift register with separate shift left and shift
right serial inputs.

    Ŀ             Ŀ
 OE 1   16 VCC          S1 S0 Function      
  D 2       15 Q3          ͵
 P3 3       14 Q2           0  0  Reset         
 P2 4       13 Q1           0  1  Shift right   
 P1 5 40104 12 Q0           1  0  Shift left    
 P0 6       11 CLK          1  1  Parallel load 
  L 7       10 S1          
GND 8        9 S0
    
#
40105
16x4 3-state asynchronous FIFO with reset.

      Ŀ
   OE 1   16 VCC
/FULL 2       15 RD
   WR 3       14 /EMPTY
   D0 4       13 Q0
   D1 5 40105 12 Q1
   D2 6       11 Q2
   D3 7       10 Q3
  GND 8        9 RST
      
#
40106
Hex inverters with schmitt-trigger inputs.
0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4 40106 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
40107
Dual 2-input open-collector NAND gates with buffered output.

    Ŀ             Ŀ           __
 1A 1    8 VCC          A  B /Y       /Y = AB
 1B 2        7 2B          ͵
/1Y 3 40107  6 2A           0  0  Z 
GND 4        5 /2Y          0  1  Z 
                  1  0  Z 
                              1  1  0 
                             
#
40108, 40208, 4580
4x4-bit 3-state synchronous triple-port register file.

      Ŀ
  1Q3 1       24 VCC
  1Q2 2           23 1Q1
  1RD 3           22 1Q0
  2Q0 4           21 2RD
  2Q1 5           20 D0
  2Q2 6           19 D1
  2Q3 7   40108   18 D2
  WA0 8           17 D3
  WA1 9           16 WCLK
 2RA1 10          15 WR
 2RA0 11          14 1RA1
  GND 12          13 1RA0
      
#
40109
Quad 3-state noninverting buffer/level shifter.
VDD

    Ŀ             Ŀ
VCC 1   16 VDD          A  OE  Y  
1OE 2       15 4OE         ͵
 1A 3       14 4A           X  0   Z  
 1Y 4       13 4Y           0  1  GND 
 2Y 5 40109 12              1  1  VDD 
 2A 6       11 3Y          
2OE 7       10 3A
GND 8        9 3OE
    
#
4011
Quad 2-input NAND gates.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
/2Y 4  4011 11 /4Y          0  1  1 
 2A 5       10 /3Y          1  0  1 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
40110
4-bit asynchronous decade up/down counter with 7-segment decoder/common-
cathode LED driver, ripple carry and borrow, separate up and down clocks,
clock enable and output latch.

       Ŀ
    YA 1   16 VCC
    YG 2       15 YB
    YF 3       14 YC
/CLKEN 4       13 YD
   RST 5 40110 12 YE
    LE 6       11 BORROW
 CLKDN 7       10 CARRY
   GND 8        9 CLKUP
       
#
4012
Dual 4-input NAND gates.

    Ŀ             Ŀ        ____
/1Y 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1A 2       13 /2Y         ͵
 1B 3       12 2D           0  X  X  X  1 
 1C 4  4012 11 2C           1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
    6        9 2A           1  1  1  0  1 
GND 7        8              1  1  1  1  0 
                 
#
4013
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
   1Q 1   14 VCC        D CLKSETRST Q /Q 
  /1Q 2       13 2Q        ͵
 1CLK 3       12 /2Q        X  X  0  1  0  1 
 1RST 4  4013 11 2CLK       X  X  1  0  1  0 
   1D 5       10 2RST       X  X  1  1  1  1 
 1SET 6        9 2D         0  /  0  0  0  1 
  GND 7        8 2SET       1  /  0  0  1  1 
                  X !/  0  0  -  - 
                             
#
4014
8-bit parallel-in serial-out shift register with three parallel outputs.

    Ŀ
 P0 1   16 VCC
 Q2 2       15 P1
 Q0 3       14 P2
 P4 4       13 P3
 P5 5  4014 12 Q1
 P6 6       11 D
 P7 7       10 CLK
GND 8        9 LD//SH
    
#
40147
10-to-4 line noninverting priority encoder.

    Ŀ
 A4 1   16 VCC
 A5 2       15 A0
 A6 3       14 Y3
 A7 4       13 A3
 A8 5 40147 12 A2
 Y2 6       11 A1
 Y1 7       10 A9
GND 8        9 Y0
    
#
4015, 744015
Dual 4-bit serial-in parallel-out shift register with asynchronous reset.

     Ŀ
2CLK 1   16 VCC
 2Q0 2       15 2D
 1Q1 3       14 2RST
 1Q2 4       13 2Q3
 1Q3 5  4015 12 2Q2
1RST 6       11 2Q1
  1D 7       10 1Q0
 GND 8        9 1CLK
     
#
4016, 4066, 744016, 744066
Quad analog switches.

     Ŀ
  1X 1   14 VCC
  1Y 2       13 1EN
  2Y 3       12 4EN
  2X 4  4016 11 4X
 2EN 5  4066 10 4Y
 3EN 6        9 3Y
 GND 7        8 3X
     
#
4017, 744017
4-bit asynchronous decade counter with fully decoded outputs, reset and both
active high and active low clocks.

    Ŀ
 Q5 1   16 VCC
 Q1 2       15 RST
 Q0 3       14 CLK1
 Q2 4       13 /CLK2
 Q6 5  4017 12 RCO
 Q7 6       11 Q9
 Q3 7       10 Q4
GND 8        9 Q8
    
#
4018
5-stage (divide by 2,4,6,8 or 10) Johnson counter with preset inputs.

    Ŀ
  D 1   16 VCC
 P1 2       15 RST
 P2 3       14 CLK
/Q2 4       13 /Q5
/Q1 5  4018 12 P5
/Q3 6       11 /Q4
 P3 7       10 PE
GND 8        9 P4
    
#
4019
8-to-4 line noninverting data selector/multiplexer with OR function.

    Ŀ             Ŀ
4A1 1   16 VCC          A0 A1 S1 S0 Y     Y=S0A0+S1A1
3A0 2       15 4A0         ͵
3A1 3       14 S1           X  X  0  0  0 
2A0 4       13 Y4           X  0  0  1  0 
2A1 5  4019 12 Y3           0  X  1  0  0 
1A0 6       11 Y2           X  1  X  1  1 
1A1 7       10 Y1           1  X  1  X  1 
GND 8        9 S0          
    
#
40194
4-bit bidirectional shift register with asynchronous reset and separate
shift left and shift right serial inputs.

     Ŀ            Ŀ
/RST 1   16 VCC         S1 S0 Function      
   D 2       15 Q3         ͵
  P3 3       14 Q2          0  0  Hold          
  P2 4       13 Q1          0  1  Shift right   
  P1 5 40194 12 Q0          1  0  Shift left    
  P0 6       11 CLK         1  1  Parallel load 
   L 7       10 S1         
 GND 8        9 S0
     
#
4020, 744020
14-bit asynchronous binary counter with reset.
Q1 and Q2 outputs missing.

    Ŀ
Q11 1   16 VCC
Q12 2       15 Q10
Q13 3       14 Q9
 Q5 4       13 Q7
 Q4 5  4020 12 Q8
 Q6 6       11 RST
 Q3 7       10 /CLK
GND 8        9 Q0
    
#
4021
8-bit parallel-in serial-out shift register with asynchronous load input
and three parallel outputs.

    Ŀ
 P0 1   16 VCC
 Q2 2       15 P1
 Q0 3       14 P2
 P4 4       13 P3
 P5 5  4021 12 Q1
 P6 6       11 D
 P7 7       10 CLK
GND 8        9 LD//SH
    
#
4022
3-bit asynchronous binary counter with fully decoded outputs, reset and both
active high and active low clocks.

    Ŀ
 Q1 1   16 VCC
 Q0 2       15 RST
 Q2 3       14 CLK1
 Q5 4       13 /CLK2
 Q6 5  4022 12 RCO
    6       11 Q4
 Q3 7       10 Q7
GND 8        9
    
#
4023
Triple 3-input NAND gates.

    Ŀ             Ŀ       ___
 1A 1   14 VCC          A  B  C /Y   /Y = ABC
 1B 2       13 3C          ͵
 2A 3       12 3B           0  X  X  1 
 2B 4  4023 11 3A           1  0  X  1 
 2C 5       10 /3Y          1  1  0  1 
/2Y 6        9 /1Y          1  1  1  0 
GND 7        8 1C          
    
#
4024, 744024
7-bit asynchronous binary counter with reset.

     Ŀ
/CLK 1   14 VCC
 RST 2       13
  Q6 3       12 Q0
  Q5 4  4024 11 Q1
  Q4 5       10
  Q3 6        9 Q2
 GND 7        8
     
#
4025
Triple 3-input NOR gates.

    Ŀ             Ŀ       _____
 1A 1   14 VCC          A  B  C /Y   /Y = A+B+C
 1B 2       13 3C          ͵
 2A 3       12 3B           0  0  0  1 
 2B 4  4025 11 3A           0  0  1  0 
 2C 5       10 /3Y          0  1  X  0 
/2Y 6        9 /1Y          1  X  X  0 
GND 7        8 1C          
    
#
4026
4-bit asynchronous decade counter with 7-segment decoder, display enable,
ripple carry, reset and both active high and active low clocks.

      Ŀ
 CLK1 1   16 VCC
/CLK2 2       15 RST
  DEI 3       14 YC'
  DEO 4       13 YC
   CO 5  4026 12 YB
   YF 6       11 YE
   YG 7       10 YA
  GND 8        9 YD
      
#
4027
Dual J-K flip-flops with set and reset.

      Ŀ           Ŀ
   1Q 1   16 VCC        J  K CLKSETRST Q /Q 
  /1Q 2       15 2Q        ͵
 1CLK 3       14 /2Q        X  X  X  1  1  1  1 
 1RST 4       13 2CLK       X  X  X  1  0  1  0 
   1K 5  4027 12 2RST       X  X  X  0  1  0  1 
   1J 6       11 2K         0  0  /  0  0  -  - 
 1SET 7       10 2J         0  1  /  0  0  0  1 
  GND 8        9 2SET       1  0  /  0  0  1  0 
                  1  1  /  0  0 /Q  Q 
                              X  X !/  0  0  -  - 
                             
#
4028
1-of-10 noninverting decoder/demultiplexer.

    Ŀ             Ŀ
 Y4 1   16 VCC          S3 S2 S1 S0 Y0 Y1... Y9
 Y2 2       15 Y3          ͵
 Y0 3       14 Y1           0  0  0  0  1  0  0  0 
 Y7 4       13 S1           0  0  0  1  0  1  0  0 
 Y9 5  4028 12 S2           .  .  .  .  0  0  .  0 
 Y5 6       11 S3           1  0  0  1  0  0  0  1 
 Y6 7       10 S0           1  0  1  X  0  0  0  0 
GND 8        9 Y8           1  1  X  X  0  0  0  0 
                 
#
4029
4-bit synchronous binary/decade up/down counter with preset and ripple carry
output.

     Ŀ
  PE 1   16 VCC
  Q4 2       15 CLK
  P4 3       14 Q3
  P1 4       13 P3
/RCI 5  4029 12 P2
  Q1 6       11 Q2
/RCO 7       10 U//D
 GND 8        9 B//D
     
#
4030
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2Y 4  4030 11 4Y           0  1  1 
 2A 5       10 3Y           1  0  1 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
4031
64-bit serial-in serial-out shift register.
S selects between D (when 0) and E serial inputs.  Y is Q delayed by half a
cycle (i.e. clocked on falling edge).

    Ŀ
  E 1   16 VCC
CLK 2       15 D
    3       14
    4       13
  Y 5  4031 12
  Q 6       11
 /Q 7       10 S
GND 8        9 CLKout
    
#
4032
Triple serial adder.
Each section can be used to add long binary words, one bit on each clock
cycle.  CRST resets the internal carry flip-flop after one clock delay.
The INV inputs can be used to invert the sum output (giving a 1's-complemented
result).

     Ŀ
  3 1   16 VCC
3INV 2       15 3A
 CLK 3       14 3B
  2 4       13 2A
2INV 5  4032 12 2B
CRST 6       11 1B
1INV 7       10 1A
 GND 8        9 1
     
#
4033
4-bit asynchronous decade counter with 7-segment decoder, ripple blanking,
ripple carry, reset and both active high and active low clocks.

      Ŀ
 CLK1 1   16 VCC
/CLK2 2       15 RST
  RBI 3       14 LT
  RBO 4       13 YC
   CO 5  4033 12 YB
   YF 6       11 YE
   YG 7       10 YA
  GND 8        9 YD
      
#
4034
8-bit bidirectional shift register with dual parallel I/O ports
and selectable synchronous/asynchronous parallel load.

     Ŀ
  A0 1       24 VCC
  A1 2           23 B0
  A2 3           22 B1
  A3 4           21 B2
  A4 5           20 B3
  A5 6           19 B4
  A6 7    4034   18 B5
  A7 8           17 B6
 ENA 9           16 B7
   D 10          15 CLK
B//A 11          14 SY//ASY
 GND 12          13 LD//SH
     
#
4035
4-bit inverting/noninverting shift register with J-/K inputs and
asynchronous reset.

       Ŀ
    Q3 1   16 VCC
  /INV 2       15 Q2
    /K 3       14 Q1
     J 4       13 Q0
   RST 5  4035 12 P0
   CLK 6       11 P1
LD//SH 7       10 P2
   GND 8        9 P3
       
#
4038
Triple negative-edge-triggered serial adder.
Each section can be used to add long binary words, one bit on each clock
cycle.  CRST resets the internal carry flip-flop after one clock delay.
The INV inputs can be used to invert the sum output (giving a 1's-complemented
result).

     Ŀ
  3 1   16 VCC
3INV 2       15 3A
/CLK 3       14 3B
  2 4       13 2A
2INV 5  4038 12 2B
CRST 6       11 1B
1INV 7       10 1A
 GND 8        9 1
     
#
4040, 744040
12-bit asynchronous binary counter with reset.

    Ŀ
Q11 1   16 VCC
 Q5 2       15 Q10
 Q4 3       14 Q9
 Q6 4       13 Q7
 Q3 5  4040 12 Q8
 Q2 6       11 RST
 Q1 7       10 /CLK
GND 8        9 Q0
    
#
4041
Quad buffers with complementary outputs.

    Ŀ             Ŀ
 1Y 1   14 VCC          A  Y /Y        Y = A
/1Y 2       13 4A          ͵
 1A 3       12 /4Y          0  0  1 
 2Y 4  4041 11 4Y           1  1  0 
/2Y 5       10 3A          
 2A 6        9 /3Y
GND 7        8 3Y
    
#
4042
4-bit transparent latch with selectable latch enable polarity and
complementary outputs.

    Ŀ             Ŀ
 Q3 1   16 VCC          LE LP D  Q /Q 
 Q0 2       15 /Q3         ͵
/Q0 3       14 D3           0  0  0  0  1 
 D0 4       13 D2           0  0  1  1  0 
 LE 5  4042 12 /Q2          1  0  X  -  - 
 LP 6       11 Q2           1  1  0  0  1 
 D2 7       10 Q1           1  1  1  1  0 
GND 8        9 /Q1          0  1  X  -  - 
                 
#
4043
Quad 3-state S-R latches with overriding set.

    Ŀ             Ŀ
 1Q 1   16 VCC          S  R  OE Q 
 2Q 2       15 1R          ͵
 2R 3       14 1S           X  X  0  Z 
 2S 4       13              0  0  1  - 
 OE 5  4043 12 4S           0  1  1  1 
 3S 6       11 4R           1  0  1  0 
 3R 7       10 4Q           1  1  1  1 
GND 8        9 3Q          
    
#
4044
Quad 3-state S-R latches with overriding reset.

    Ŀ             Ŀ
 1Q 1   16 VCC          S  R  OE Q 
    2       15 4S          ͵
 2S 3       14 4R           X  X  0  Z 
 2R 4       13 2Q           0  0  1  - 
 OE 5  4044 12 4R           0  1  1  1 
 3S 6       11 4S           1  0  1  0 
 3R 7       10 4Q           1  1  1  0 
GND 8        9 3Q          
    
#
4045
21-bit asynchronous binary counter with oscillator and reset input.
Only two 3% duty cycle outputs (180 out of phase) from the last counter stage
are available.  Can be used to generate a 1Hz clock signal using a 2.097152MHz
crystal.  P and N MOSFET source connections from the oscillator inverter are
brought out of the package to allow the use of source resistors, but usually
pS=VCC and nS=GND.

    Ŀ
 pS 1   16 X1
 nS 2       15 X0
VCC 3       14 GND
    4       13
    5  4045 12
    6       11
 QA 7       10
 QB 8        9
    
#
4046, 744046
Phase Locked Loop.

       Ŀ
PCPout 1   16 VCC
PC1out 2       15 Zener
 PCinB 3       14 PCinA
VCOout 4       13 PC2out
   /EN 5  4046 12 R2
   C1A 6       11 R1
   C1B 7       10 SFout
   GND 8        9 VCOin
       
#
4047
Low-power astable/monostable multivibrator with oscillator output.

      Ŀ
 Cext 1   14 VCC
 Rext 2       13 OSC
RCext 3       12 RETRIG
 /AST 4  4047 11 /Q
  AST 5       10 Q
  /TR 6        9 RST
  GND 7        8 TR
      
#
4048
3-state 8-input multifunction gate.

    Ŀ             Ŀ
  Y 1   16 VCC          S2 S1 S0 OE Output function        
 OE 2       15 X           ͵
  A 3       14 H            X  X  X  0  Z                      
  B 4       13 G            0  0  0  1  8-input NOR            
  C 5  4048 12 F            0  0  1  1  8-input OR             
  D 6       11 E            0  1  0  1  2-wide 4-input OR-AND  
 S1 7       10 S2           0  1  1  1  2-wide 4-input OR-NAND 
GND 8        9 S0           1  0  0  1  8-input AND            
                  1  0  1  1  8-input NAND           
                              1  1  0  1  2-wide 4-input AND-NOR 
                              1  1  1  1  2-wide 4-input AND-OR  
                             
#
4049, 744049
Hex inverters with high-to-low level shifter inputs.

    Ŀ             Ŀ               _
VCC 1   16              A /Y           /Y = A
/Y1 2       15 /Y6         ͵
 A1 3       14 A6           0  1 
/Y2 4       13              1  0 
 A2 5  4049 12 /Y5         
/Y3 6       11 A5
 A3 7       10 /Y4
GND 8        9 A4
    
#
4050, 744050
Hex buffers with high-to-low level shifter inputs.

    Ŀ             Ŀ
VCC 1   16              A  Y            Y = A
 Y1 2       15 Y6          ͵
 A1 3       14 A6           0  0 
 Y2 4       13              1  1 
 A2 5  4050 12 Y5          
 Y3 6       11 A5
 A3 7       10 Y4
GND 8        9 A4
    
#
4051, 744051
8-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    Ŀ
 X4 1   16 VCC
 X6 2       15 X2
  Y 3       14 X1
 X7 4       13 X0
 X5 5  4051 12 X3
/EN 6       11 S0
VEE 7       10 S1
GND 8        9 S2
    
#
4052, 744052
8-to-2 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    Ŀ
1X0 1   16 VCC
1X2 2       15 2X2
 1Y 3       14 2X1
1X3 4       13 2Y
1X1 5  4052 12 2X0
/EN 6       11 2X3
VEE 7       10 S0
GND 8        9 S1
    
#
4053, 744053
Triple 2-to-1 line analog multiplexer/demultiplexer with dual power supply.
VEE supply may not be more positive than GND.

    Ŀ
1X0 1   16 VCC
1X1 2       15 1Y
2X1 3       14 3Y
 2Y 4       13 3X1
2X0 5  4053 12 3X0
/EN 6       11 3S
VEE 7       10 1S
GND 8        9 2S
    
#
4054
Quad level shifters/LCD drivers with input latches.
A level-shifted inverse of the  (phase) input should be connected to the
backplane of the LCD; this can be done by using one section of the 4054
with A=0 and LE=1.

    Ŀ             Ŀ            _ 
1LE 1   16 VCC          LE A  R        Y = R$
   2       15 1A          ͵
 1Y 3       14 2LE          0  X  - 
 2Y 4       13 2A           1  0  0 
 3Y 5  4054 12 3LE          1  1  1 
 4Y 6       11 3A          
VEE 7       10 4LE
GND 8        9 4A
    
#
4055
BCD to 7-segment decoder/LCD driver.
The o (phase) output should be connected to the backplane of the LCD.

    Ŀ
 o 1   16 VCC
 A2 2       15 YF
 A1 3       14 YG
 A3 4       13 YE
 A0 5  4055 12 YD
 i 6       11 YC
VEE 7       10 YB
GND 8        9 YA
    
#
4056
BCD to 7-segment decoder/LCD driver with input latches.
A level-shifted inverse of the  (phase) input should be connected to the
backplane of the LCD.

    Ŀ
 LE 1   16 VCC
 A2 2       15 YF
 A1 3       14 YG
 A3 4       13 YE
 A0 5  4056 12 YD
   6       11 YC
VEE 7       10 YB
GND 8        9 YA
    
#
4059
Divide by N counter.
Ka, Kb, Kc are the modulus (divide by number) of the 1st and last
counting sections. N can range from 3 to 15999.  The down-counter
is preset by 15 jam inputs.

    Ŀ
CLK 1       24 VCC
 LD 2           23 Q
 J1 3           22 J5
 J2 4           21 J6
 J3 5           20 J7
 J4 6           19 J8
J16 7    4059   18 J9
J15 8           17 J10
J14 9           16 J11
J13 10          15 J12
 Kc 11          14 Ka
GND 12          13 Kb
    
#
4060, 744060
14-bit asynchronous binary counter with oscillator and reset input.
Q0,Q1,Q2 and Q10 outputs are missing.

    Ŀ
Q11 1   16 VCC
Q12 2       15 Q9
Q13 3       14 Q7
 Q5 4       13 Q8
 Q4 5  4060 12 RST
 Q6 6       11 X1
 Q3 7       10 X0
GND 8        9 X2
    
#
4063
4-bit noninverting magnitude comparator with cascade inputs.

     Ŀ
  B3 1   16 VCC
IA<B 2       15 A3
IA=B 3       14 B2
IA>B 4       13 A2
OA>B 5  4063 12 A1
OA=B 6       11 B1
OA<B 7       10 A0
 GND 8        9 B0
     
#
4067, 744067
16-to-1 line analog multiplexer/demultiplexer.

    Ŀ
  Y 1       24 VCC
 X7 2           23 X8
 X6 3           22 X9
 X5 4           21 X10
 X4 5           20 X11
 X3 6           19 X12
 X2 7    4067   18 X13
 X1 8           17 X14
 X0 9           16 X15
 S0 10          15 /EN
 S1 11          14 S2
GND 12          13 S3
    
#
4068
8-input AND/NAND gate with complementary outputs.

    Ŀ
  Y 1   14 VCC         Y = ABCDEFGH
  A 2       13 /Y
  B 3       12 H
  C 4  4068 11 G
  D 5       10 F
    6        9 E
GND 7        8
    
#
4069
Hex inverters.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4  4069 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
4070
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2Y 4  4070 11 4Y           0  1  1 
 2A 5       10 3Y           1  0  1 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
4071
Quad 2-input OR gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = A+B
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  0 
/2Y 4  4071 11 /4Y          0  1  1 
 2A 5       10 /3Y          1  0  1 
 2B 6        9 3B           1  1  1 
GND 7        8 3A          
    
#
4072
Dual 4-input OR gates.

    Ŀ             Ŀ
 1Y 1   14 VCC          A  B  C  D /Y    Y = A+B+C+D
 1A 2       13 2Y          ͵
 1B 3       12 2D           0  0  0  0  0 
 1C 4  4072 11 2C           0  0  0  1  1 
 1D 5       10 2B           0  0  1  X  1 
    6        9 2A           0  1  X  X  1 
GND 7        8              1  X  X  X  1 
                 
#
4073
Triple 3-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  C  Y    Y = ABC
 1B 2       13 3A          ͵
 2A 3       12 3B           0  X  X  0 
 2B 4  4073 11 3C           1  0  X  0 
 2C 5       10 3Y           1  1  0  0 
 2Y 6        9 1Y           1  1  1  1 
GND 7        8 1C          
    
#
4075, 744075
Triple 3-input OR gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  C  Y    Y = A+B+C
 1B 2       13 3A          ͵
 2A 3       12 3B           0  0  0  0 
 2B 4  4075 11 3C           0  0  1  1 
 2C 5       10 3Y           0  1  X  1 
 2Y 6        9 1Y           1  X  X  1 
GND 7        8 1C          
    
#
4076
4-bit 3-state D flip-flop with reset, dual clock enables and dual
output enables.

     Ŀ
/OE1 1   16 VCC
/OE2 2       15 RST
  Q0 3       14 D0
  Q1 4       13 D1
  Q2 5  4076 12 D2
  Q3 6       11 D3
 CLK 7       10 /CLKEN1
 GND 8        9 /CLKEN2
     
#
4077
Quad 2-input XNOR gates.

    Ŀ             Ŀ            _ 
 1A 1   14 VCC          A  B /Y        Y = A$B
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
/2Y 4  4077 11 /4Y          0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  1 
GND 7        8 3A          
    
#
4078, 744078
8-input OR/NOR gate with complementary outputs.

    Ŀ
  Y 1   14 VCC         Y=A+B+C+D+E+F+G+H
  A 2       13 /Y
  B 3       12 H
  C 4  4078 11 G
  D 5       10 F
    6        9 E
GND 7        8
    
#
4081
Quad 2-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2Y 4  4081 11 4Y           0  1  0 
 2A 5       10 3Y           1  0  0 
 2B 6        9 3B           1  1  1 
GND 7        8 3A          
    
#
4082
Dual 4-input AND gates.

    Ŀ             Ŀ
 1Y 1   14 VCC          A  B  C  D  Y     Y = ABCD
 1A 2       13 2Y          ͵
 1B 3       12 2D           0  X  X  X  0 
 1C 4  4082 11 2C           1  0  X  X  0 
 1D 5       10 2B           1  1  0  X  0 
    6        9 2A           1  1  1  0  0 
GND 7        8              1  1  1  1  1 
                 
#
4085
Dual 3-wide 2/1-input AND-NOR gates.

    Ŀ                 _______
 1A 1   14 VCC        /Y = AB+CD+E
 1B 2       13 1D
/1Y 3       12 1C
/2Y 4  4085 11 1E
 2A 5       10 2E
 2B 6        9 2D
GND 7        8 2C
    
#
4086
6-wide 2/1-input AND-NOR gate.

    Ŀ                 ________________
  A 1   14 VCC        /Y = AB+CD+EF+GH+J+/K
  B 2       13 H
 /Y 3       12 G
    4  4086 11 K
  C 5       10 J
  D 6        9 F
GND 7        8 E
    
#
4089
4-bit synchronous binary rate multiplier.

     Ŀ
 Q15 1   16 VCC
  D2 2       15 D1
  D3 3       14 D0
 SET 4       13 RST
  /Q 5  4089 12 CASC
   Q 6       11 CIN
COUT 7       10 STB
 GND 8        9 CLK
     
#
4093
Quad 2-input NAND gates with schmitt-trigger inputs.
0.9V typical input hysteresis at VCC=+5V and 2.3V at VCC=+10V.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
/2Y 4  4093 11 /4Y          0  1  1 
 2A 5       10 /3Y          1  0  1 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
4094
8-bit 3-state serial-in/parallel-out shift register with output latches.
Y is Q0 delayed by half a cycle (i.e. clocked on falling edge).

    Ŀ
 LE 1   16 VCC
  D 2       15 OE
CLK 3       14 P3
 P7 4       13 P2
 P6 5  4094 12 P1
 P5 6       11 P0
 P4 7       10 Y
GND 8        9 Q0
    
#
4095
J-K flip-flop with triple ANDed J an K inputs, set and reset.

     Ŀ            Ŀ
     1   14 VCC        J1J2J3K1K2K3CLKSETRST Q /Q 
 RST 2       13 SET        ͵
  J1 3       12 CLK            X       X    X  1  1  0  0 
  J2 4  4095 11 K3             X       X    X  1  0  1  0 
  J3 5       10 K2             X       X    X  0  1  0  1 
  /Q 6        9 K1             0       0    /  0  0  -  - 
 GND 7        8 Q              0       1    /  0  0  0  1 
                     1       0    /  0  0  1  0 
                                 1       1    /  0  0 /Q  Q 
                                 X       X   !/  0  0  -  - 
                             
#
4096
J-K flip-flop with triple ANDed J an K inputs (one inverted), set and reset.

     Ŀ            Ŀ
     1   14 VCC        J1J2/J3K1K2/K3CLKSETRST Q /Q 
 RST 2       13 SET        ͵
  J1 3       12 CLK            X        X     X  1  1  0  0 
  J2 4  4095 11 K1             X        X     X  1  0  1  0 
 /J3 5       10 K2             X        X     X  0  1  0  1 
  /Q 6        9 /K3            0        0     /  0  0  -  - 
 GND 7        8 Q              0        1     /  0  0  0  1 
                     1        0     /  0  0  1  0 
                                 1        1     /  0  0 /Q  Q 
                                 X        X    !/  0  0  -  - 
                             
#
4097
16-to-2 line analog multiplexer/demultiplexer.

    Ŀ
 1Y 1       24 VCC
1X7 2           23 2X0
1X6 3           22 2X1
1X5 4           21 2X2
1X4 5           20 2X3
1X3 6           19 2X4
1X2 7    4097   18 2X5
1X1 8           17 2Y
1X0 9           16 2X6
 S0 10          15 2X7
 S1 11          14 S2
GND 12          13 /EN
    
#
4098
Dual monostable multivibrator, retriggerable, resettable.

       Ŀ
 1Cext 1   16 VCC
1RCext 2       15 2Cext
  1RST 3       14 2RCext
   1TR 4       13 2RST
  /1TR 5  4098 12 2TR
    1Q 6       11 /2TR
   /1Q 7       10 2Q
   GND 8        9 /2Q
       
#
4099
1-of-8 addressable latch with reset.

    Ŀ
 Q7 1   16 VCC
RST 2       15 Q6
  D 3       14 Q5
/WR 4       13 Q4
 A0 5  4099 12 Q3
 A1 6       11 Q2
 A2 7       10 Q1
GND 8        9 Q0
    
#
41256, 41257
256kx1 DRAM.

      Ŀ
   A8 1   16 GND
    D 2       15 /CAS
  /WE 3       14 Q
 /RAS 4 41256 13 A6
   A0 5 41257 12 A3
   A2 6       11 A4
   A1 7       10 A5
  VCC 8        9 A7
      
#
4164
64kx1 DRAM.

     Ŀ
     1   16 GND
   D 2       15 /CAS
 /WE 3       14 Q
/RAS 4  4164 13 A6
  A0 5       12 A3
  A2 6       11 A4
  A1 7       10 A5
 VCC 8        9 A7
     

#
421000, 421001, 421002
1Mx1 DRAM.

     Ŀ
   D 1   18 GND
 /WE 2       17 Q
/RAS 3       16 /CAS
     4       15 A9
  A0 5   42  14 A8
  A1 6  100x 13 A7
  A2 7       12 A6
  A3 8       11 A5
 VCC 9       10 A4
     
#
424100
4Mx1 DRAM.

     Ŀ
   D 1   26 GND
 /WE 2       25 Q
/RAS 3       24 /CAS
     4       23
 A10 5       22 A9
               
       424100  
               
  A0 9       18 A8
  A1 10      17 A7
  A2 11      16 A6
  A3 12      15 A5
 VCC 13      14 A4
     
#
424400
1Mx4 DRAM.

     Ŀ
  D0 1   26 GND
  D1 2       25 D3
 /WE 3       24 D2
/RAS 4       23 /CAS
  A9 5       22 /OE
               
       424400  
               
  A0 9       18 A8
  A1 10      17 A7
  A2 11      16 A6
  A3 12      15 A5
 VCC 13      14 A4
     
#
4316, 744316
Quad analog switches with enable input and dual power supply.
VEE supply may not be more positive than GND.

    Ŀ
 1X 1   16 VCC
 1Y 2       15 1EN
 2Y 3       14 4EN
 2X 4       13 4X
2EN 5  4316 12 4Y
3EN 6       11 3Y
 EN 7       10 3X
GND 8        9 VEE
    
#
4351, 744351
8-to-1 line analog multiplexer/demultiplexer with address latch and dual
power supply.
VEE supply may not be more positive than GND.

    Ŀ
1X0 1   18 VCC
1X1 2       17 X2
2X1 3       16 X1
 2Y 4       15 X0
2X0 5  4351 14 X3
/EN 6       13 S0
 EN 7       12 S1
VEE 8       11 S2
GND 9       10 LE
    
#
4352, 744352
8-to-2 line analog multiplexer/demultiplexer with address latch and dual
power supply.
VEE supply may not be more positive than GND.

    Ŀ
1X0 1   18 VCC
1X2 2       17 2X2
 1Y 3       16 2X1
1X3 4       15 2Y
1X1 5  4352 14 2X0
/EN 6       13 2X3
 EN 7       12 S0
VEE 8       11 S1
GND 9       10 LE
    
#
4353, 744353
Triple 2-to-1 line analog multiplexer/demultiplexer with address latch and
dual power supply.
VEE supply may not be more positive than GND.

    Ŀ
1X0 1   18 VCC
1X1 2       17 1Y
2X1 3       16 3Y
 2Y 4       15 3X1
2X0 5  4353 14 3X0
/EN 6       13 3S
 EN 7       12 1S
VEE 8       11 2S
GND 9       10 LE
    
#
44256, 44258
256kx4 DRAM.

     Ŀ
  D0 1   20 GND
  D1 2       19 D3
 /WE 3       18 D2
/RAS 4       17 /CAS
     5 44256 16 /OE
  A0 6 44258 15 A8
  A1 7       14 A7
  A2 8       13 A6
  A3 9       12 A5
 VCC 10      11 A4
     
#
4464
64kx4 DRAM.

     Ŀ
 /OE 1   18 GND
  D0 2       17 D3
  D1 3       16 /CAS
 /WE 4       15 D2
/RAS 5  4464 14 A0
  A6 6       13 A1
  A5 7       12 A2
  A4 8       11 A3
 VCC 9       10 A7
     
#
4500
Industrial Control Unit.
If you _really_ want to use this RRRRISC, try to get the 'MC14500B Industrial
Control Unit Handbook' from Motorola (sorry, no ISBN number).

    Ŀ
RST 1   16 VCC
 WR 2       15 RR
  D 3       14 X0
 I3 4       13 X1
 I2 5  4500 12 JMP
 I1 6       11 RTN
 I0 7       10 FLG0
GND 8        9 FLGF
    
#
4502
6-bit 3-state inverting buffer/line driver with NOR inputs.

    Ŀ             Ŀ
 A0 1   16 VCC         /OE A  B /Y 
/Y0 2       15 A5          ͵
 A1 3       14 /Y5          1  X  X  Z 
/OE 4       13 A4           0  0  0  1 
/Y1 5  4502 12 B            0  1  0  0 
 A2 6       11 /Y4          0  X  1  0 
/Y2 7       10 A3          
GND 8        9 /Y3
    
#
4503
2/4-bit 3-state noninverting buffer/line driver.

     Ŀ            Ŀ
/1OE 1   16 VCC        /OE A  Y 
 1A1 2       15 /2OE       ͵
 1Y1 3       14 2A2         1  X  Z 
 1A2 4       13 2Y2         0  0  0 
 1Y2 5  4503 12 2A1         0  1  1 
 1A3 6       11 2Y1        
 1Y3 7       10 1A4
 GND 8        9 1Y4
     
#
4508
Dual 4-bit 3-state transparent latch with reset.

     Ŀ        Ŀ
1RST 1       24 VCC    /OE LE D  Q 
 1LE 2           23 2Q3    ͵
/1OE 3           22 2D3     1  X  X  Z 
 1D0 4           21 2Q2     0  0  X  - 
 1Q0 5           20 2D2     0  1  0  0 
 1D1 6           19 2Q1     0  1  1  1 
 1Q1 7    4508   18 2D1    
 1D2 8           17 2Q0
 1Q2 9           16 2D0
 1D3 10          15 /2OE
 1Q3 11          14 2LE
 GND 12          13 2RST
     
#
4510
4-bit synchronous binary up/down counter with asynchronous load, reset and
ripple carry output.

     Ŀ
  LD 1   16 VCC
  Q3 2       15 CLK
  P3 3       14 Q2
  P0 4       13 P2
/RCI 5  4510 12 P1
  Q0 6       11 Q1
/RCO 7       10 UP//DN
 GND 8        9 RST
     
#
4511, 744511
BCD to 7-segment decoder/common-cathode LED driver.

    Ŀ
 A1 1   16 VCC
 A2 2       15 YF
/LT 3       14 YG
/BI 4       13 YA
/LE 5  4511 12 YB
 A3 6       11 YC
 A0 7       10 YD
GND 8        9 YE
    
#
4512
8-to-1 line 3-state data selector/multiplexer with AND inputs.

    Ŀ
 A0 1   16 VCC         Y = An/B
 A1 2       15 /OE
 A2 3       14 Y
 A3 4       13 S2
 A4 5  4512 12 S1
 A5 6       11 S0
 A6 7       10 /B
GND 8        9 A7
    
#
4514, 744514
1-of-16 noninverting decoder/demultiplexer with address latches.

    Ŀ
 LE 1   24 VCC
 S0 2       23 /EN
 S1 3       22 S3
 Y7 4       21 S2
 Y6 5       20 Y10
 Y5 6       19 Y11
 Y4 7  4514 18 Y8
 Y3 8       17 Y9
 Y2 9       16 Y15
 Y1 10      15 Y14
 Y0 11      14 Y13
GND 12      13 Y12
    
#
4515, 744515
1-of-16 inverting decoder/demultiplexer with address latches.

    Ŀ
 LE 1   24 VCC
 S0 2       23 /EN
 S1 3       22 S3
/Y7 4       21 S2
/Y6 5       20 /Y10
/Y5 6       19 /Y11
/Y4 7  4515 18 /Y8
/Y3 8       17 /Y9
/Y2 9       16 /Y15
/Y1 10      15 /Y14
/Y0 11      14 /Y13
GND 12      13 /Y12
    
#
4516
4-bit synchronous decade up/down counter with asynchronous load, reset and
ripple carry output.

     Ŀ
  LD 1   16 VCC
  Q3 2       15 CLK
  P3 3       14 Q2
  P0 4       13 P2
/RCI 5  4516 12 P1
  Q0 6       11 Q1
/RCO 7       10 UP//DN
 GND 8        9 RST
     
#
4517
Dual 64-bit 3-state serial-in serial-out shift register with 4 serial
in/outputs.

     Ŀ
1Q48 1   16 VCC
1Q16 2       15 2Q48
 1WR 3       14 2Q16
1CLK 4       13 2WR
 1Q0 5  4517 12 2CLK
1Q32 6       11 2Q0
  1D 7       10 2Q32
 GND 8        9 2D
     
#
4518, 744518
Dual 4-bit asynchronous decade counters with reset and both active high and
active low clocks.

      Ŀ
 1CLK 1   16 VCC
/1CLK 2       15 2RST
  1Q0 3       14 2Q3
  1Q1 4       13 2Q2
  1Q2 5  4518 12 2Q1
  1Q3 6       11 2Q0
 1RST 7       10 /2CLK
  GND 8        9 2CLK
      
#
4520, 744520
Dual 4-bit asynchronous binary counters with reset and both active high and
active low clocks.

      Ŀ
 1CLK 1   16 VCC
/1CLK 2       15 2RST
  1Q0 3       14 2Q3
  1Q1 4       13 2Q2
  1Q2 5  4520 12 2Q1
  1Q3 6       11 2Q0
 1RST 7       10 /2CLK
  GND 8        9 2CLK
      
#
4527
4-bit synchronous decade rate multiplier.

     Ŀ
  Q9 1   16 VCC
  D2 2       15 D1
  D3 3       14 D0
SET9 4       13 RST
  /Q 5  4527 12 CASC
   Q 6       11 CIN
COUT 7       10 STB
 GND 8        9 CLK
     
#
4532
8-to-3 line noninverting priority encoder with cascade inputs.

    Ŀ
 A4 1   16 VCC
 A5 2       15 EO
 A6 3       14 GS
 A7 4       13 A3
 EI 5  4532 12 A2
 Y2 6       11 A1
 Y1 7       10 A0
GND 8        9 Y0
    
#
4536
24-bit programmable frequency divider/digital timer with oscillator,
set and reset inputs.  Digitally programmable from 2^1 to 2^24.
Connect MONO via a >10k resistor to ground for square wave output,
or to a RC network (R to VCC) for a controlled output pulse width.
Maximum guaranteed clock frequency is 500kHz at VCC=+5V (what a pity!!!).

        Ŀ
    SET 1   16 VCC
    RST 2       15 MONO
     X1 3       14 /XEN
     X0 4       13 Q
     X2 5  4536 12 S3
/DIV256 6       11 S2
  CLKEN 7       10 S1
    GND 8        9 S0
        
#
4538, 744538
Dual precision monostable multivibrator with Schmitt-trigger inputs.
Retriggerable, resettable.
For 74HC4538 the Cext pin may be grounded.

       Ŀ
 1Cext 1   16 VCC
1RCext 2       15 2Cext
  1RST 3       14 2RCext
   1TR 4       13 2RST
  /1TR 5  4538 12 2TR
    1Q 6       11 /2TR
   /1Q 7       10 2Q
   GND 8        9 /2Q
       
#
4543, 744543
BCD to 7-segment decoder/LCD driver with input latch.
The  (phase) input should be connected to the backplane of the LCD.

    Ŀ
 LE 1   16 VCC
 A2 2       15 YF
 A1 3       14 YG
 A3 4       13 YE
 A0 5  4543 12 YD
   6       11 YC
 BI 7       10 YB
GND 8        9 YA
    
#
4555
Dual 1-of-4 noninverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0 Y0 Y1 Y2 Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  0  0  0  0 
 1Y0 4       13 2S1         0  0  0  1  0  0  0 
 1Y1 5  4555 12 2Y0         0  0  1  0  1  0  0 
 1Y2 6       11 2Y1         0  1  0  0  0  1  0 
 1Y3 7       10 2Y2         0  1  1  0  0  0  1 
 GND 8        9 2Y3        
     
#
4556
Dual 1-of-4 inverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0/Y0/Y1/Y2/Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  1  1  1  1 
/1Y0 4       13 2S1         0  0  0  0  1  1  1 
/1Y1 5  4556 12 /2Y0        0  0  1  1  0  1  1 
/1Y2 6       11 /2Y1        0  1  0  1  1  0  1 
/1Y3 7       10 /2Y2        0  1  1  1  1  1  0 
 GND 8        9 /2Y3       
     
#
4585
4-bit noninverting magnitude comparator with cascade inputs.

     Ŀ
  B2 1   16 VCC
  A2 2       15 A3
OA=B 3       14 B3
IA>B 4       13 OA>B
IA<B 5  4585 12 OA<B
IA=B 6       11 B0
  A1 7       10 A0
 GND 8        9 B1
     
#
4599
1-of-8 addressable latch with readback and reset.

    Ŀ
 Q7 1   18 VCC
RST 2       17 Q6
  D 3       16 Q5
/WR 4       15 Q4
 A0 5  4599 14 Q3
 A1 6       13 Q2
 A2 7       12 Q1
 CE 8       11 Q0
GND 9       10 /RD
    
#
551000
128kx8 SRAM.

    Ŀ
    1       32 VCC
A16 2           31 A15
A14 3           30 CE2
A12 4           29 /WE
 A7 5           28 A13
 A6 6           27 A8
 A5 7           26 A9
 A4 8   551000  25 A11
 A3 9           24 /OE
 A2 10          23 A10
 A1 11          22 /CE
 A0 12          21 D7
 D0 13          20 D6
 D1 14          19 D5
 D2 15          18 D4
GND 16          17 D3
    
#
55256
32kx8 SRAM.

    Ŀ
A14 1       28 VCC
A12 2           27 /WE
 A7 3           26 A13
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7   55256   22 /OE
 A2 8           21 A10
 A1 9           20 /CE
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
555, 7555
Universal timer.

     Ŀ 
 GND 1    8 VCC
  TR 2        7 Dis
   Q 3  555   6 Thr
/RST 4        5 CV
      
#
556
Dual 555 universal timers.

      Ŀ
 1Dis 1   14 VCC
 1Thr 2       13 2Dis
  1CV 3       12 2Thr
/1RST 4  556  11 2CV
   1Q 5       10 /2RST
  1TR 6        9 2Q
  GND 7        8 2TR
      
#
5564
8kx8 SRAM.

    Ŀ
    1       28 VCC
A12 2           27 /WE
 A7 3           26 CE2
 A6 4           25 A8
 A5 5           24 A9
 A4 6           23 A11
 A3 7    5564   22 /OE
 A2 8           21 A10
 A1 9           20 /CE1
 A0 10          19 D7
 D0 11          18 D6
 D1 12          17 D5
 D2 13          16 D4
GND 14          15 D3
    
#
558
Quad monostable timers.

       Ŀ
    1Q 1   16 4Q
1RCext 2       15 4RCext
   1TR 3       14 4TR
    CV 4       13 /RST
   VCC 5  558  12 GND
   2TR 6       11 3TR
2RCext 7       10 3RCext
    2Q 8        9 3Q
       
#
5911
Serial 128x8/64x16 EEPROM.

    Ŀ
 CD 1    8 VCC
CLK 2        7 RDY//BSY
 DI 3  5911  6 x16//x8
 DO 4        5 GND
    
#
6502, 65SC02
Mostek 6502 CPU.

      Ŀ
  GND 1       40 /RST
  RDY 2           39 2
   1 3           38 /SO
 /IRQ 4           37 0 (in)
      5           36
 /NMI 6           35
 SYNC 7           34 R//W
  VCC 8           33 D0
   A0 9           32 D1
   A1 10   6502   31 D2
   A2 11  65SC02  30 D3
   A3 12          29 D4
   A4 13          28 D5
   A5 14          27 D6
   A6 15          26 D7
   A7 16          25 A15
   A8 17          24 A14
   A9 18          23 A13
  A10 19          22 A12
  A11 20          21 GND
      
#
6551
Asynchronous serial interface controller (Rockwell).

     Ŀ
 GND 1       28 R//W
 CS0 2           27 CLK
/CS1 3           26 /IRQ
/RST 4           25 D7
 RxC 5           24 D6
  X1 6           23 D5
  X0 7    6551   22 D4
/RTS 8           21 D3
/CTS 9           20 D2
 TxD 10          19 D1
/DTR 11          18 D0
 RxD 12          17 /DSR
 RS0 13          16 /DCD
 RS1 14          15 VCC
     
#
68000, 68010 (DIP)
Motorola 16/32-bit microprocessor.

       Ŀ
    D4 1       64 D5
    D3 2           63 D6
    D2 3           62 D7
    D1 4           61 D8
    D0 5           60 D9
   /AS 6           59 D10
  /UDS 7           58 D11
  /LDS 8           57 D12
  R//W 9           56 D13
/DTACK 10          55 D14
   /BG 11          54 D15
/BGACK 12          53 GND
   /BR 13          52 A23
   VCC 14          51 A22
   CLK 15          50 A21
   GND 16  68000   49 VCC
 /HALT 17  68010   48 A20
  /RST 18          47 A19
  /VMA 19          46 A18
     E 20          45 A17
  /VPA 21          44 A16
 /BERR 22          43 A15
 /IPL2 23          42 A14
 /IPL1 24          41 A13
 /IPL0 25          40 A12
   FC2 26          39 A11
   FC1 27          38 A10
   FC0 28          37 A9
    A1 29          36 A8
    A2 30          35 A7
    A3 31          34 A6
    A4 32          33 A5
       
#
68000, 68010 (PLCC)
Motorola 16/32-bit microprocessor.

PLCC68
Ŀ
 10 /DTACK      27 /IPL0       44 A13         61 D12        
 11 /BG         28 FC2         45 A14         62 D11        
 12 /BGACK      29 FC1         46 A15         63 D10        
 13 /BR         30 FC0         47 A16         64 D9         
 14 VCC         31             48 A17         65 D8         
 15 CLK         32 A1          49 A18         66 D7         
 16 GND         33 A2          50 A19         67 D6         
 17 GND         34 A3          51 A20         68 D5         
 18             35 A4          52 VCC          1 D4         
 19 /HALT       36 A5          53 A21          2 D3         
 20 /RST        37 A6          54 A22          3 D2         
 21 /VMA        38 A7          55 A23          4 D1         
 22 E           39 A8          56 GND          5 D0         
 23 /VPA        40 A9          57 GND          6 /AS        
 24 /BERR       41 A10         58 D15          7 /UDS       
 25 /IPL2       42 A11         59 D14          8 /LDS       
 26 /IPL1       43 A12         60 D13          9 R//W       

#
68008 (DIP)
Motorola 16-bit microprocessor with 8-bit data bus.

    Ŀ
 A3 1       48 A2
 A4 2           47 A0
 A5 3           46 A0
 A6 4           45 FC0
 A7 5           44 FC1
 A8 6           43 FC2
 A9 7           42 /IPL02
A10 8           41 /IPL1
A11 9           40 /BERR
A12 10          39 /VPA
A13 11          38 E
A14 12          37 /RST
VCC 13  68008   36 /HALT
A15 14          35 GND
GND 15          34 CLK
A16 16          33 /BR
A17 17          32 /BG
A18 18          31 /DTACK
A19 19          30 R//W
 D7 20          29 /DS
 D6 21          28 /AS
 D5 22          27 D0
 D4 23          26 D1
 D3 24          25 D2
    
#
68008 (PLCC)
Motorola 16-bit microprocessor with 8-bit data bus.

PLCC52
Ŀ
  8 A9          21 A19         34 /DTACK      47 /IPL0      
  9 A10         22 A20         35 /BG         48 FC2        
 10 A11         23 D7          36 /BGACK      49 FC1        
 11 A12         24 D6          37 /BR         50 FC0        
 12 A13         25 D5          38 CLK         51 A0         
 13 A21         26 D4          39 GND         52 A1         
 14 A14         27 D3          40 /HALT        1 A2         
 15 VCC         28 D2          41 /RST         2 A3         
 16 A15         29 D1          42 E            3 A4         
 17 GND         30 D0          43 /VPA         4 A5         
 18 A16         31 /AS         44 /BERR        5 A6         
 19 A17         32 /DS         45 /IPL1        6 A7         
 20 A18         33 R//W        46 /IPL2        7 A8         

#
6802
Motorola 6802 CPU.

      Ŀ
  GND 1       40 /RST
/HALT 2           39 EXTAL
   MR 3           38 XTAL
 /IRQ 4           37 E
  VMA 5           36 RAMEN
 /NMI 6           35 VCC_RAM
   BA 7           34 R//W
  VCC 8           33 D0
   A0 9           32 D1
   A1 10    MC    31 D2
   A2 11   6802   30 D3
   A3 12          29 D4
   A4 13          28 D5
   A5 14          27 D6
   A6 15          26 D7
   A7 16          25 A15
   A8 17          24 A14
   A9 18          23 A13
  A10 19          22 A12
  A11 20          21 GND
      
#
6809, 6309
Motorola 6809 and Hitachi 63C09 CPU.

      Ŀ
  GND 1       40 /HALT
 /NMI 2           39 EXTAL
 /IRQ 3           38 XTAL
/FIRQ 4           37 /RST
   BS 5           36 MRDY
   BA 6           35 Q
  VCC 7           34 E
   A0 8           33 /BREQ
   A1 9           32 R//W
   A2 10  MC6809  31 D0
   A3 11  H63C09  30 D1
   A4 12          29 D2
   A5 13          28 D3
   A6 14          27 D4
   A7 15          26 D5
   A8 16          25 D6
   A9 17          24 D7
  A10 18          23 A15
  A11 19          22 A14
  A12 20          21 A13
      
#
68153
680x0 family bus interrupter.

       Ŀ
   VCC 1       40 A3
  R//W 2           39 A2
   /CE 3           38 A1
/DTACK 4           37 D7
 /IACK 5           36 D6
/IACKi 6           35 D5
/IACKo 7           34 D4
 /IRQ1 8           33 D3
   GND 9           32 D2
   GND 10          31 GND
   VCC 11  68153   30 VCC
 /IRQ2 12          29 D1
 /IRQ3 13          28 D0
 /IRQ4 14          27 /INTAE
 /IRQ5 15          26 INTAL1
 /IRQ6 16          25 INTAL0
 /IRQ7 17          24 /INT3
   CLK 18          23 /INT2
 /INT0 19          22 /INT1
   GND 20          21 VCC
       
#
68230 (DIP)
680x0 family Parallel Interface and Timer (PI/T)

    Ŀ
 D5 1       48 D4
 D6 2           47 D3
 D7 3           46 D2
PA0 4           45 D1
PA1 5           44 D0
PA2 6           43 R//W
PA3 7           42 /DTACK
PA4 8           41 /CE
PA5 9           40 CLK
PA6 10          39 /RST
PA7 11          38 GND
VCC 12          37 PC7 /TIACK
 H1 13  68230   36 PC6 /PIACK
 H2 14          35 PC5 /PIRQ
 H3 15          34 PC4 /DMAREQ
 H4 16          33 PC3 TOUT
PB0 17          32 PC2 TIN
PB1 18          31 PC1
PB2 19          30 PC0
PB3 20          29 RS0
PB4 21          28 RS1
PB5 22          27 RS2
PB6 23          26 RS3
PB7 24          25 RS4
    
#
68230 (PLCC)
680x0 family Parallel Interface and Timer (PI/T)

PLCC52
Ŀ
  8             21             34 PC0         47 R//W       
  9 PA4         22 PB2         35 PC1         48 D0         
 10 PA5         23 PB3         36 PC2 TIN     49 D1         
 11 PA6         24 PB4         37 PC3 TOUT    50 D2         
 12 PA7         25 PB5         38 PC4 /DMARQ  51 D3         
 13 VCC         26 PB6         39 PC5 /PIRQ   52 D4         
 14 H1          27 PB7         40 PC6 /PIACK   1 D5         
 15 H2          28 A4          41 PC7 /TIACK   2 D6         
 16 H3          29 A3          42 GND          3 D7         
 17 H4          30 A2          43 /RST         4 PA0        
 18 PB0         31 A1          44 CLK          5 PA1        
 19 PB1         32 A0          45 /CE          6 PA2        
 20             33             46 /DTACK       7 PA3        

#
6845
CRT Controller.

       Ŀ
   GND 1       40 VSYNC
  /RST 2           39 HSYNC
 LPSTB 3           38 RA0
   MA0 4           37 RA1
   MA1 5           36 RA2
   MA2 6           35 RA3
   MA3 7           34 RA4
   MA4 8           33 D0
   MA5 9           32 D1
   MA6 10   6845   31 D2
   MA7 11   CRTC   30 D3
   MA8 12          29 D4
   MA9 13          28 D5
  MA10 14          27 D6
  MA11 15          26 D7
  MA12 16          25 /CE
  MA13 17          24 A0
DISPEN 18          23 IORQ
CURSOR 19          22 R/W
   VCC 20          21 CLK
       
#
68452
680x0 family bus arbiter.

       Ŀ
   VCC 1       28 GND
   VCC 2           27 /BCLR
  /GT4 3           26 /GT0
 /REQ3 4           25 /REQ4
  /GT5 5           24 /GT1
 /REQ2 6           23 /REQ5
 /REQ1 7           22 /REQ6
   GND 8   68452   21 /REQ7
 /REQ0 9           20 /BG
  /LEI 10          19 /BR
/BGACK 11          18 /GT2
  /GT7 12          17 /GT3
  /GT6 13          16 VCC
   GND 14          15 VCC
       
#
68901 (DIP)
680x0 multi-function peripheral.

     Ŀ
R//W 1       48 /CE
 RS0 2           47 /DS
 RS1 3           46 /DTACK
 RS2 4           45 /IACK
 RS3 5           44 D7
 RS4 6           43 D6
  TC 7           42 D5
  SO 8           41 D4
  SI 9           40 D3
  RC 10          39 D2
 VCC 11          38 D1
     12          37 D0
 TAO 13  68901   36 GND
 TBO 14          35 CLK
 TCO 15          34 /IEI
 TDO 16          33 /IEO
  X1 17          32 /IRQ
  X0 18          31 /RR
 TAI 19          30 /TR
 TBI 20          29 INT7
/RST 21          28 INT6
INT0 22          27 INT5
INT1 23          26 INT4
INT2 24          25 INT3
     
#
68901 (PLCC)
680x0 multi-function peripheral.

PLCC52
Ŀ
  8 TC          21             34 /TR         47 D6         
  9 SO          22 TAI         35 /RR         48 D7         
 10 SI          23 TBI         36 /IRQ        49 /IACK      
 11 RC          24 /RST        37 /IEO        50 /DTACK     
 12 VCC         25 INT0        38 /IEI        51 /DS        
 13             26 INT1        39 CLK         52 /CE        
 14             27 INT2        40 GND          1            
 15 TAO         28 INT3        41 D0           2 R//W       
 16 TBO         29 INT4        42 D1           3 RS0        
 17 TCO         30 INT5        43 D2           4 RS1        
 18 TDO         31 INT6        44 D3           5 RS2        
 19 X1          32 INT7        45 D4           6 RS3        
 20 X0          33             46 D5           7 RS4        

#
6N135
Optocoupler with IR diode and transistor output configuration.

  Ŀ
  1    8 VCC
A 2        7 B
K 3  6N135 6 C
  4        5 E
  
#
6N138
Optocoupler with IR diode and darlington transistor output configuration.

  Ŀ
  1    8 VCC
A 2        7 B
K 3  6N138 6 C
  4        5 E
  
#
7400
Quad 2-input NAND gates.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4  7400 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
7401
Quad 2-input open-collector NAND gates.

    Ŀ             Ŀ           __
/1Y 1   14 VCC          A  B /Y       /Y = AB
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  Z 
/2Y 4  7401 11 4A           0  1  Z 
 2A 5       10 /3Y          1  0  Z 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
7402
Quad 2-input NOR gates.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  1 
/2Y 4  7402 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
7403
Quad 2-input open-collector NAND gates.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  Z 
 2A 4  7403 11 /4Y          0  1  Z 
 2B 5       10 3B           1  0  Z 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
7404
Hex inverters.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4  7404 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
7405
Hex open-collector inverters.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  Z 
/2Y 4  7405 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
7406
Hex open-collector high-voltage inverters.
Maximum output voltage is 30V.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  Z 
/2Y 4  7406 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
7407
Hex open-collector high-voltage buffers.
Maximum output voltage is 30V.

    Ŀ             Ŀ
 1A 1   14 VCC          A  Y            Y = A
 1Y 2       13 6A          ͵
 2A 3       12 6Y           0  0 
 2Y 4  7407 11 5A           1  Z 
 3A 5       10 5Y          
 3Y 6        9 4A
GND 7        8 4Y
    
#
7408
Quad 2-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7408 11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    
#
7409
Quad 2-input open-collector AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7409 11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  Z 
GND 7        8 3Y          
    
#
741
Universal operational amplifier.

     Ŀ
NULL 1    8 
 -In 2        7 VCC
 +In 3  741   6 OUT
 VEE 4        5 NULL
     
#
7410
Triple 3-input NAND gates.

    Ŀ             Ŀ       ___
 1A 1   14 VCC          A  B  C /Y   /Y = ABC
 1B 2       13 1C          ͵
 2A 3       12 /1Y          0  X  X  1 
 2B 4  7410 11 3C           1  0  X  1 
 2C 5       10 3B           1  1  0  1 
/2Y 6        9 3A           1  1  1  0 
GND 7        8 /3Y         
    
#
741000
Quad 2-input NAND gates with buffered output.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3  7410 12 4A           0  0  1 
 2A 4   00  11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
741004
Hex inverters with buffered output.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3  7410 12 /6Y          0  Z 
/2Y 4   04  11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
741005
Hex open-collector inverters with buffered output.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3  7410 12 /6Y          0  Z 
/2Y 4   05  11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
741032
Quad 2-input OR gates with buffered output.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = A+B
 1B 2       13 4B          ͵
 1Y 3  7410 12 4A           0  0  0 
 2A 4   32  11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    
#
74107
Dual negative-edge-triggered J-K flip-flops with reset.

    Ŀ             Ŀ
 1J 1   14 VCC          J  K /CLK/RST Q /Q 
/1Q 2       13 /1RST       ͵
 1Q 3   74  12 /1CLK        X  X   X   0  0  1 
 1K 4  107  11 2K           0  0   \   1  -  - 
 2Q 5       10 /2RST        0  1   \   1  0  1 
/2Q 6        9 /2CLK        1  0   \   1  1  0 
GND 7        8 2J           1  1   \   1 /Q  Q 
                  X  X  !\   1  -  - 
                             
#
74109
Dual J-/K flip-flops with set and reset.

      Ŀ           Ŀ
/1RST 1   16 VCC        J /K CLK/SET/RST Q /Q 
   1J 2       15 /2RST     ͵
  /1K 3       14 2J         X  X  X   0   0  1  1 
 1CLK 4   74  13 /2K        X  X  X   0   1  1  0 
/1SET 5  109  12 2CLK       X  X  X   1   0  0  1 
   1Q 6       11 /2SET      0  0  /   1   1  0  1 
  /1Q 7       10 2Q         0  1  /   1   1  -  - 
  GND 8        9 /2Q        1  0  /   1   1 /Q  Q 
                  1  1  /   1   1  1  0 
                              X  X !/   1   1  -  - 
                             
#
7411
Triple 3-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  C  Y    Y = ABC
 1B 2       13 1C          ͵
 2A 3       12 1Y           0  X  X  0 
 2B 4  7411 11 3C           1  0  X  0 
 2C 5       10 3B           1  1  0  0 
 2Y 6        9 3A           1  1  1  1 
GND 7        8 3Y          
    
#
7411000
Quad 2-input NAND gates with buffered output.

    Ŀ             Ŀ           __
 1A 1   16 1B           A  B /Y       /Y = AB
/1Y 2       15 2A          ͵
/2Y 3       14 2B           0  0  1 
GND 4  7411 13 VCC          0  1  1 
GND 5   000 12 VCC          1  0  1 
/3Y 6       11 3A           1  1  0 
/4Y 7       10 3B          
 4B 8        9 4A
    
#
7411002
Quad 2-input NOR gates with buffered output.

    Ŀ             Ŀ           ___
 1A 1   16 1B           A  B /Y       /Y = A+B
/1Y 2       15 2A          ͵
/2Y 3       14 2B           0  0  1 
GND 4  7411 13 VCC          0  1  0 
GND 5   002 12 VCC          1  0  0 
/3Y 6       11 3A           1  1  0 
/4Y 7       10 3B          
 4B 8        9 4A
    
#
7411004
Hex inverters with buffered output.

    Ŀ             Ŀ               _
/1Y 1   20 1A           A /Y           /Y = A
/2Y 2       19 2A          ͵
/3Y 3       18 3A           0  1 
GND 4       17              1  0 
GND 5  7411 16 VCC         
GND 6   004 15 VCC
GND 7       14
/4Y 8       13 4A
/5Y 9       12 5A
/6Y 10      11 6A
    
#
7411008
Quad 2-input AND gates with buffered output.

    Ŀ             Ŀ
 1A 1   16 1B           A  B  Y        Y = AB
 1Y 2       15 2A          ͵
 2Y 3       14 2B           0  0  0 
GND 4  7411 13 VCC          0  1  0 
GND 5   008 12 VCC          1  0  0 
 3Y 6       11 3A           1  1  1 
 4Y 7       10 3B          
 4B 8        9 4A
    
#
7411010
Triple 3-input NAND gates with buffered output.

    Ŀ             Ŀ       ___
 1A 1   16 1B           A  B  C /Y   /Y = ABC
/1Y 2       15 1C          ͵
/2Y 3       14 2A           0  X  X  1 
GND 4  7411 13 VCC          1  0  X  1 
GND 5   010 12 VCC          1  1  0  1 
/3Y 6       11 2B           1  1  1  0 
 3C 7       10 2C          
 3B 8        9 3A
    
#
7411011
Triple 3-input AND gates with buffered output.

    Ŀ             Ŀ
 1A 1   16 1B           A  B  C  Y    Y = ABC
 1Y 2       15 1C          ͵
 2Y 3       14 2A           0  X  X  0 
GND 4  7411 13 VCC          1  0  X  0 
GND 5   011 12 VCC          1  1  0  0 
 3Y 6       11 2B           1  1  1  1 
 3C 7       10 2C          
 3B 8        9 3A
    
#
7411013
Dual 4-input NAND gates with schmitt-trigger inputs and buffered output.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ        ____
 1B 1   14              A  B  C  D /Y    /Y = ABCD
 1A 2       13 1C          ͵
/1Y 3  7411 12 1D           0  X  X  X  1 
GND 4   013 11 VCC          1  0  X  X  1 
/2Y 5       10 2A           1  1  0  X  1 
 2D 6        9 2B           1  1  1  0  1 
 2C 7        8              1  1  1  1  0 
                 
#
7411014
Hex inverters with schmitt-trigger inputs and buffered output.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ               _
/1Y 1   20 1A           A /Y           /Y = A
/2Y 2       19 2A          ͵
/3Y 3       18 3A           0  1 
GND 4       17              1  0 
GND 5  7411 16 VCC         
GND 6   014 15 VCC
GND 7       14
/4Y 8       13 4A
/5Y 9       12 5A
/6Y 10      11 6A
    
#
7411020
Dual 4-input NAND gates with buffered output.

    Ŀ             Ŀ        ____
 1B 1   14              A  B  C  D /Y    /Y = ABCD
 1A 2       13 1C          ͵
/1Y 3       12 1D           0  X  X  X  1 
GND 4  7411 11 VCC          1  0  X  X  1 
/2Y 5   020 10 2A           1  1  0  X  1 
 2D 6        9 2B           1  1  1  0  1 
 2C 7        8              1  1  1  1  0 
                 
#
7411021
Dual 4-input AND gates with buffered output.

    Ŀ             Ŀ
 1B 1   14              A  B  C  D  Y     Y = ABCD
 1A 2       13 1C          ͵
 1Y 3       12 1D           0  X  X  X  0 
GND 4  7411 11 VCC          1  0  X  X  0 
 2Y 5   021 10 2A           1  1  0  X  0 
 2D 6        9 2B           1  1  1  0  0 
 2C 7        8              1  1  1  1  1 
                 
#
7411027
Triple 3-input NOR gates with buffered output.

    Ŀ             Ŀ       _____
 1A 1   16 1B           A  B  C /Y   /Y = A+B+C
/1Y 2       15 1C          ͵
/2Y 3       14 2A           0  0  0  1 
GND 4 7411  13 VCC          0  0  1  0 
GND 5  027  12 VCC          0  1  X  0 
/3Y 6       11 2B           1  X  X  0 
 3C 7       10 2C          
 3B 8        9 3A
    
#
7411030
8-input NAND gate with buffered output.

    Ŀ                 ________
  C 1   14 D          /Y = ABCDEFGH
  B 2       13 E
  A 3 7411  12 F
GND 4  030  11 VCC
 /Y 5       10
    6        9 G
    7        8 H
    
#
7411032
Quad 2-input OR gates with buffered output.

    Ŀ             Ŀ
 1A 1   16 1B           A  B  Y        Y = A+B
 1Y 2       15 2A          ͵
 2Y 3       14 2B           0  0  0 
GND 4 7411  13 VCC          0  1  1 
GND 5  032  12 VCC          1  0  1 
 3Y 6       11 3A           1  1  1 
 4Y 7       10 3B          
 4B 8        9 4A
    
#
7411034
Hex buffers.

    Ŀ             Ŀ
 1Y 1   20 1A           A  Y            Y = A
 2Y 2       19 2A          ͵
 3Y 3       18 3A           0  0 
GND 4       17              1  1 
GND 5 7411  16 VCC         
GND 6  034  15 VCC
GND 7       14
 4Y 8       13 4A
 5Y 9       12 5A
 6Y 10      11 6A
    
#
7411074
Dual D flip-flops with set and reset.

      Ŀ           Ŀ
/1SET 1   14 1CLK       D CLK/SET/RST Q /Q 
   1Q 2       13 1D        ͵
  /1Q 3 7411  12 /1RST      X  X   0   0  1  1 
  GND 4  074  11 VCC        X  X   0   1  1  0 
  /2Q 5       10 /2RST      X  X   1   0  0  1 
   2Q 6        9 2D         0  /   1   1  0  1 
/2SET 7        8 2CLK       1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             
#
7411086
Quad 2-input XOR gates with buffered output.

    Ŀ             Ŀ                    _   _
 1A 1   16 1B           A  B  Y        Y = A$B = (AB)+(AB)
 1Y 2       15 2B          ͵
 2Y 3       14 2A           0  0  0 
GND 4 7411  13 VCC          0  1  1 
GND 5  086  12 VCC          1  0  1 
 3Y 6       11 3B           1  1  0 
 4Y 7       10 3A          
 4A 8        9 4B
    
#
7411109
Dual J-/K flip-flops with set and reset.

      Ŀ           Ŀ
/1SET 1   16 1CLK       J /K CLK/SET/RST Q /Q 
   1Q 2       15 /1K       ͵
  /1Q 3       14 1J         X  X  X   0   0  1  1 
  GND 4 7411  13 /1RST      X  X  X   0   1  1  0 
  /2Q 5  109  12 VCC        X  X  X   1   0  0  1 
   2Q 6       11 /2RST      0  0  /   1   1  0  1 
/2SET 7       10 2J         0  1  /   1   1  -  - 
 2CLK 8        9 /2K        1  0  /   1   1 /Q  Q 
                  1  1  /   1   1  1  0 
                              X  X !/   1   1  -  - 
                             
#
7411112
Dual negative-edge-triggered J-K flip-flops with set and reset.

      Ŀ           Ŀ
/1SET 1   16 1J         J  K /CLK/SET/RST Q /Q 
   1Q 2       15 1K        ͵
  /1Q 3       14 /1CLK      X  X   X   0   0  0  0 
  GND 4 7411  13 /1RST      X  X   X   0   1  1  0 
  /2Q 5  112  12 VCC        X  X   X   1   0  0  1 
   2Q 6       11 /2RST      0  0   \   1   1  -  - 
/2SET 7       10 /2CLK      0  1   \   1   1  0  1 
   2J 8        9 2K         1  0   \   1   1  1  0 
                  1  1   \   1   1 /Q  Q 
                              X  X  !\   1   1  -  - 
                             
#
7411132
Quad 2-input NAND gates with schmitt-trigger inputs and buffered output.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ           __
 1A 1   16 1B           A  B /Y       /Y = AB
/1Y 2       15 2A          ͵
/2Y 3       14 2B           0  0  1 
GND 4  7411 13 VCC          0  1  1 
GND 5   132 12 VCC          1  0  1 
/3Y 6       11 3A           1  1  0 
/4Y 7       10 3B          
 4B 8        9 4A
    
#
7411138
1-of-8 inverting decoder/demultiplexer.

    Ŀ             Ŀ
/Y1 1   16 /Y0         EN1/EN2/EN3 S2 S1 S0/Y0/Y1.../Y7
/Y2 2       15 S0          ͵
/Y3 3       14 S1           0  X    X  X  X  X  1  1  1  1 
GND 4 7411  13 S2           1  1    X  X  X  X  1  1  1  1 
/Y4 5  138  12 VCC          1  0    1  X  X  X  1  1  1  1 
/Y5 6       11 EN1          1  0    0  0  0  0  0  1  1  1 
/Y6 7       10 /EN2         1  0    0  0  0  1  1  0  1  1 
/Y7 8        9 /EN3         1  0    0  .  .  .  1  1  .  1 
                  1  0    0  1  1  1  1  1  1  0 
                             
#
7411139
Dual 1-of-4 inverting decoder/demultiplexer.

     Ŀ            Ŀ
/1Y1 1   16 /1Y0       /EN S1 S0/Y0/Y1/Y2/Y3
/1Y2 2       15 1S0        ͵
/1Y3 3       14 1S1         1  X  X  1  1  1  1 
 GND 4 7411  13 /1EN        0  0  0  0  1  1  1 
/2Y0 5  139  12 VCC         0  0  1  1  0  1  1 
/2Y1 6       11 /2EN        0  1  0  1  1  0  1 
/2Y2 7       10 2S0         0  1  1  1  1  1  0 
/2Y3 8        9 2S1        
     
#
7411151
8-to-1 line data selector/multiplexer with complementary outputs.

    Ŀ
 A0 1   16 A1
/EN 2       15 A2
  Y 3       14 A3
GND 4 7411  13 A4
 /Y 5  151  12 VCC
 S0 6       11 A5
 S1 7       10 A6
 S2 8        9 A7
    
#
7411153
8-to-2 line noninverting data selector/multiplexer with separate enables.

     Ŀ
  S0 1   16 1A0
  S1 2       15 1A1
  1Y 3       14 1A2
 GND 4 7411  13 1A3
  2Y 5  153  12 VCC
/1EN 6       11 2A0
/2EN 7       10 2A1
 2A3 8        9 2A2
     
#
7411157
8-to-4 line noninverting data selector/multiplexer.

    Ŀ
  S 1   20 1A0
 1Y 2       19 1A1
 2Y 3       18 2A0
GND 4       17 2A1
GND 5 7411  16 VCC
GND 6  157  15 VCC
GND 7       14 3A0
 3Y 8       13 3A1
 4Y 9       12 4A0
/EN 10      11 4A1
    
#
7411158
8-to-4 line inverting data selector/multiplexer.

    Ŀ
  S 1   20 1A0
/1Y 2       19 1A1
/2Y 3       18 2A0
GND 4       17 2A1
GND 5 7411  16 VCC
GND 6  158  15 VCC
GND 7       14 3A0
/3Y 8       13 3A1
/4Y 9       12 4A0
/EN 10      11 4A1
    
#
7411160
4-bit synchronous decade counter with load, asynchronous reset, and ripple
carry output.

      Ŀ
  RCO 1   20 /RST
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  160  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 ENP
/LOAD 10      11 ENT
      
#
7411161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

      Ŀ
  RCO 1   20 /RST
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  161  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 ENP
/LOAD 10      11 ENT
      
#
7411162
4-bit synchronous decade counter with load, reset, and ripple carry output.

      Ŀ
  RCO 1   20 /RST
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  162  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 ENP
/LOAD 10      11 ENT
      
#
7411163
4-bit synchronous binary counter with load, reset, and ripple carry output.

      Ŀ
  RCO 1   20 /RST
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  163  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 ENP
/LOAD 10      11 ENT
      
#
7411169
4-bit synchronous binary up/down counter with load and ripple carry output.

      Ŀ
 /RCO 1   20 U//D
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  169  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 /ENP
/LOAD 10      11 /ENT
      
#
7411174
6-bit D flip-flop with reset.

    Ŀ             Ŀ
 Q1 1   20 /RST        /RSTCLK D  Q 
 Q2 2       19 D1          ͵
 Q3 3       18 D2            0  X  X  0 
GND 4       17 D3            1  /  0  0 
GND 5 7411  16 VCC           1  /  1  1 
GND 6  174  15 VCC           1 !/  X  - 
GND 7       14 D4          
 Q4 8       13 D5
 Q5 9       12 D6
 Q6 10      11 CLK
    
#
7411175
4-bit D flip-flop with complementary outputs and reset.

    Ŀ             Ŀ
/Q1 1   20 Q1          /RSTCLK D  Q /Q 
 Q2 2       19 /RST        ͵
/Q2 3       18 D1            0  X  X  0  1 
GND 4       17 D2            1  /  0  0  1 
GND 5 7411  16 VCC           1  /  1  1  0 
GND 6  175  15 VCC           1 !/  X  -  - 
GND 7       14 D3          
 Q3 8       13 D4
/Q3 9       12 CLK
 Q4 10      11 /Q4
    
#
7411181
4-bit 16-function arithmetic logic unit (ALU)

     Ŀ
 CIN 1   28 /A0
   M 2       27 /A1
 A=B 3       26 /A2
 /F0 4       25 /A3
 /F1 5       24 /B0
 GND 6       23 /B1
 GND 7  7411 22 VCC
 GND 8   181 21 VCC
 GND 9       20 /B2
 /F2 10      19 /B3
 /F3 11      18 S0
  /P 12      17 S1
  /G 13      16 S2
COUT 14      15 S3
     
#
7411190
4-bit synchronous decade up/down counter with load and both carry out and
ripple clock outputs.

      Ŀ
/RCLK 1   20 U//D
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  190  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 /CLKEN
 /RCO 10      11 /LOAD
      
#
7411191
4-bit synchronous binary up/down counter with load and both carry out and
ripple clock outputs.

      Ŀ
/RCLK 1   20 U//D
   Q0 2       19 CLK
   Q1 3       18 P0
  GND 4       17 P1
  GND 5 7411  16 VCC
  GND 6  191  15 VCC
  GND 7       14 P2
   Q2 8       13 P3
   Q3 9       12 /CLKEN
 /RCO 10      11 /LOAD
      
#
7411194
4-bit bidirectional universal shift register with asynchronous reset and
separate shift left and shift right serial inputs.

    Ŀ
 SA 1   20 S0
 QA 2       19 S1
 QB 3       18 A
GND 4       17 B
GND 5 7411  16 VCC
GND 6  194  15 VCC
GND 7       14 C
 QC 8       13 D
 QD 9       12 /RST
 SD 10      11 CLK
    
#
74112
Dual negative-edge-triggered J-K flip-flops with set and reset.

      Ŀ           Ŀ
/1CLK 1   16 VCC        J  K /CLK/SET/RST Q /Q 
   1K 2       15 /1RST     ͵
   1J 3       14 /2RST      X  X   X   0   0  0  0 
/1SET 4   74  13 /2CLK      X  X   X   0   1  1  0 
   1Q 5  112  12 2K         X  X   X   1   0  0  1 
  /1Q 6       11 2J         0  0   \   1   1  -  - 
  /2Q 7       10 /2SET      0  1   \   1   1  0  1 
  GND 8        9 2Q         1  0   \   1   1  1  0 
                  1  1   \   1   1 /Q  Q 
                              X  X  !\   1   1  -  - 
                             
#
7411238
1-of-8 noninverting decoder/demultiplexer.

    Ŀ             Ŀ
 Y1 1   16 Y0          EN1/EN2/EN3 S2 S1 S0/Y0/Y1.../Y7
 Y2 2       15 S0          ͵
 Y3 3       14 S1           0  X    X  X  X  X  0  0  0  0 
GND 4 7411  13 S2           1  1    X  X  X  X  0  0  0  0 
 Y4 5  238  12 VCC          1  0    1  X  X  X  0  0  0  0 
 Y5 6       11 EN1          1  0    0  0  0  0  1  0  0  0 
 Y6 7       10 /EN2         1  0    0  0  0  1  0  1  0  0 
 Y7 8        9 /EN3         1  0    0  .  .  .  0  0  .  0 
                  1  0    0  1  1  1  0  0  0  1 
                             
#
7411239
Dual 1-of-4 noninverting decoder/demultiplexer.

    Ŀ             Ŀ
1Y1 1   16 1Y0         /EN S1 S0 Y0 Y1 Y2 Y3
1Y2 2       15 1S0         ͵
1Y3 3       14 1S1          1  X  X  0  0  0  0 
GND 4 7411  13 /1EN         0  0  0  1  0  0  0 
2Y0 5  239  12 VCC          0  0  1  0  1  0  0 
2Y1 6       11 /2EN         0  1  0  0  0  1  0 
2Y2 7       10 2S0          0  1  1  0  0  0  1 
2Y3 8        9 2S1         
    
#
7411240
Dual 4-bit 3-state inverting buffer/line driver.

     Ŀ
/1Y1 1   24 /1OE
/1Y2 2       23 1A1
/1Y3 3       22 1A2
/1Y4 4       21 1A3
 GND 5       20 1A4
 GND 6  7411 19 VCC
 GND 7  240  18 VCC
 GND 8       17 2A1
/2Y1 9       16 2A2
/2Y2 10      15 2A3
/2Y3 11      14 2A4
/2Y4 12      13 /2OE
     
#
7411241
Dual 4-bit 3-state noninverting buffer/line driver.
One active low, one active high output enable.

    Ŀ
1Y1 1   24 /1OE
1Y2 2       23 1A1
1Y3 3       22 1A2
1Y4 4       21 1A3
GND 5       20 1A4
GND 6  7411 19 VCC
GND 7  241  18 VCC
GND 8       17 2A1
2Y1 9       16 2A2
2Y2 10      15 2A3
2Y3 11      14 2A4
2Y4 12      13 2OE
    
#
7411244
Dual 4-bit 3-state noninverting buffer/line driver.

    Ŀ
1Y1 1   24 /1OE
1Y2 2       23 1A1
1Y3 3       22 1A2
1Y4 4       21 1A3
GND 5       20 1A4
GND 6  7411 19 VCC
GND 7  244  18 VCC
GND 8       17 2A1
2Y1 9       16 2A2
2Y2 10      15 2A3
2Y3 11      14 2A4
2Y4 12      13 /2OE
    
#
7411245
8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ             Ŀ
 A1 1   24 DIR         /ENDIR A  B 
 A2 2       23 B1          ͵
 A3 3       22 B2           1  X  Z  Z 
 A4 4       21 B3           0  0  B  Z 
GND 5       20 B4           0  1  Z  A 
GND 6  7411 19 VCC         
GND 7  245  18 VCC
GND 8       17 B5
 A5 9       16 B6
 A6 10      15 B7
 A7 11      14 B8
 A8 12      13 /EN
    
#
7411251
8-to-1 line 3-state data selector/multiplexer with complementary outputs.

    Ŀ
 A0 1   16 A1
/OE 2       15 A2
  Y 3       14 A3
GND 4 7411  13 A4
 /Y 5  251  12 VCC
 S0 6       11 A5
 S1 7       10 A6
 S2 8        9 A7
    
#
7411253
8-to-2 line 3-state noninverting data selector/multiplexer.

     Ŀ
  S0 1   16 1A0
  S1 2       15 1A1
  1Y 3       14 1A2
 GND 4 7411  13 1A3
  2Y 5  253  12 VCC
/1EN 6       11 2A0
/2EN 7       10 2A1
 2A3 8        9 2A2
     
#
7411257
8-to-4 line 3-state noninverting data selector/multiplexer.

    Ŀ
  S 1   20 1A0
 1Y 2       19 1A1
 2Y 3       18 2A0
GND 4       17 2A1
GND 5 7411  16 VCC
GND 6  257  15 VCC
GND 7       14 3A0
 3Y 8       13 3A1
 4Y 9       12 4A0
/EN 10      11 4A1
    
#
7411258
8-to-4 line 3-state inverting data selector/multiplexer.

    Ŀ
  S 1   20 1A0
/1Y 2       19 1A1
/2Y 3       18 2A0
GND 4       17 2A1
GND 5 7411  16 VCC
GND 6  258  15 VCC
GND 7       14 3A0
/3Y 8       13 3A1
/4Y 9       12 4A0
/EN 10      11 4A1
    
#
7411273
8-bit D flip-flop with reset.

    Ŀ             Ŀ
 Q1 1   24 /RST        /RSTCLK D  Q 
 Q2 2       23 D1          ͵
 Q3 3       22 D2            0  X  X  0 
 Q4 4       21 D3            1  /  0  0 
GND 5       20 D4            1  /  1  1 
GND 6 7411  19 VCC           1 !/  X  - 
GND 7  273  18 VCC         
GND 8       17 D5
 Q5 9       16 D6
 Q6 10      15 D7
 Q7 11      14 D8
 Q8 12      13 CLK
    
#
7411280
9-bit odd/even parity generator/checker.

     Ŀ
  A0 1   14 A8
  A1 2       13 A7
 ODD 3 7411  12 A6
 GND 4  280  11 VCC
EVEN 5       10 A5
     6        9 A4
  A2 7        8 A3
     
#
7411286
9-bit odd/even parity generator/checker with bus driver parity I/O port.

      Ŀ
   A0 1   14 A8
   A1 2       13 A7
 PI/O 3 7411  12 A6
  GND 4  286  11 VCC
ERROR 5       10 A5
/XMIT 6        9 A4
   A2 7        8 A3
      
#
7411299
8-bit 3-state bidirectional universal shift/storage register with asynchronous
reset and with separate shift left and shift right serial inputs.  Multiplexed
parallel I/O.

    Ŀ
 PA 1   24 QA
 PB 2       23 S0
 PC 3       22 S1
 PD 4       21 /OE1
GND 5       20 /OE2
GND 6 7411  19 VCC
GND 7  299  18 VCC
GND 8       17 SA
 PE 9       16 SH
 PF 10      15 CLK
 PG 11      14 /RST
 PH 12      13 QH
    
#
74113
Dual negative-edge-triggered J-K flip-flop with set.

      Ŀ           Ŀ
/1CLK 1   14 VCC        J  K /CLK/SET Q /Q 
   1K 2       13 /2CLK     ͵
   1J 3  74   12 2K         X  X   X   0  1  0 
/1SET 4  113  11 2J         X  X   X   1  0  1 
   1Q 5       10 /2SET      0  0   \   1  -  - 
  /1Q 6        9 2Q         0  1   \   1  0  1 
  GND 7        8 /2Q        1  0   \   1  1  0 
                  1  1   \   1 /Q  Q 
                              X  X  !\   1  -  - 
                             
#
7411323
8-bit 3-state bidirectional universal shift/storage register with reset and
with separate shift left and shift right serial inputs.  Multiplexed
parallel I/O.

    Ŀ
 PA 1   24 QA
 PB 2       23 S0
 PC 3       22 S1
 PD 4       21 /OE1
GND 5       20 /OE2
GND 6 7411  19 VCC
GND 7  323  18 VCC
GND 8       17 SA
 PE 9       16 SH
 PF 10      15 CLK
 PG 11      14 /RST
 PH 12      13 QH
    
#
7411352
8-to-2 line inverting data selector/multiplexer with separate enables.

     Ŀ
  S0 1   16 1A0
  S1 2       15 1A1
 /1Y 3       14 1A2
 GND 4 7411  13 1A3
 /2Y 5  352  12 VCC
/1EN 6       11 2A0
/2EN 7       10 2A1
 2A3 8        9 2A2
     
#
7411353
8-to-2 line 3-state inverting data selector/multiplexer with separate enables.

     Ŀ
  S0 1   16 1A0
  S1 2       15 1A1
 /1Y 3       14 1A2
 GND 4 7411  13 1A3
 /2Y 5  353  12 VCC
/1EN 6       11 2A0
/2EN 7       10 2A1
 2A3 8        9 2A2
     
#
7411373
8-bit 3-state transparent latch.

    Ŀ             Ŀ
 Q1 1   24 /OE         /OE LE D  Q 
 Q2 2       23 D1          ͵
 Q3 3       22 D2           1  X  X  Z 
 Q4 4       21 D3           0  0  X  - 
GND 5       20 D4           0  1  0  0 
GND 6 7411  19 VCC          0  1  1  1 
GND 7  373  18 VCC         
GND 8       17 D5
 Q5 9       16 D6
 Q6 10      15 D7
 Q7 11      14 D8
 Q8 12      13 LE
    
#
7411374
8-bit 3-state D flip-flop.

    Ŀ             Ŀ
 Q1 1   24 /OE         /OECLK D  Q 
 Q2 2       23 D1          ͵
 Q3 3       22 D2           1  X  X  Z 
 Q4 4       21 D3           0  /  0  0 
GND 5       20 D4           0  /  1  1 
GND 6 7411  19 VCC          0 !/  X  - 
GND 7  374  18 VCC         
GND 8       17 D5
 Q5 9       16 D6
 Q6 10      15 D7
 Q7 11      14 D8
 Q8 12      13 CLK
    
#
7411377
8-bit D flip-flop with clock enable.

    Ŀ             Ŀ
 Q1 1   24 /CLKEN      /CENCLK D  Q 
 Q2 2       23 D1          ͵
 Q3 3       22 D2            1  X  X  - 
 Q4 4       21 D3            0  /  0  0 
GND 5       20 D4            0  /  1  1 
GND 6 7411  19 VCC           0 !/  X  - 
GND 7  377  18 VCC         
GND 8       17 D5
 Q5 9       16 D6
 Q6 10      15 D7
 Q7 11      14 D8
 Q8 12      13 CLK
    
#
7411378
6-bit D flip-flop with clock enable.

    Ŀ             Ŀ
 Q1 1   20 /CLKEN      /CENCLK D  Q 
 Q2 2       19 D1          ͵
 Q3 3       18 D2            1  X  X  - 
GND 4       17 D3            0  /  0  0 
GND 5 7411  16 VCC           0  /  1  1 
GND 6  378  15 VCC           0 !/  X  - 
GND 7       14 D4          
 Q4 8       13 D5
 Q5 9       12 D6
 Q6 10      11 CLK
    
#
7411379
4-bit D flip-flop with complementary outputs and clock enable.

    Ŀ             Ŀ
/Q1 1   20 Q1          /CENCLK D  Q /Q 
 Q2 2       19 /CLKEN      ͵
/Q2 3       18 D1            1  X  X  -  - 
GND 4       17 D2            0  /  0  0  1 
GND 5 7411  16 VCC           0  /  1  1  0 
GND 6  379  15 VCC           0 !/  X  -  - 
GND 7       14 D3          
 Q3 8       13 D4
/Q3 9       12 CLK
 Q4 10      11 /Q4
    
#
74114
Dual negative-edge-triggered J-K flip-flop with set, common clock and
common reset.

      Ŀ           Ŀ
 /RST 1   14 VCC        J  K /CLK/SET/RST Q /Q 
   1K 2       13 /CLK      ͵
   1J 3  74   12 2K         X  X   X   0   0  ?  ? 
/1SET 4  114  11 2J         X  X   X   0   1  1  0 
   1Q 5       10 /2SET      X  X   X   1   0  0  1 
  /1Q 6        9 2Q         0  0   \   1   1  -  - 
  GND 7        8 /2Q        0  1   \   1   1  0  1 
                  1  0   \   1   1  1  0 
                              1  1   \   1   1 /Q  Q 
                              X  X  !\   1   1  -  - 
                             
#
7411478
8-bit 3-state dual-ranking D flip-flop.
Designed to prevent metastable conditions in data synchronization
applications in which setup and hold times may be violated.

    Ŀ
 Q1 1   24 /OE
 Q2 2       23 D1
 Q3 3       22 D2
 Q4 4       21 D3
GND 5       20 D4
GND 6 7411  19 VCC
GND 7  478  18 VCC
GND 8       17 D5
 Q5 9       16 D6
 Q6 10      15 D7
 Q7 11      14 D8
 Q8 12      13 CLK
    
#
7411520
8-bit inverting identity comparator with integrated 20k pull-up resistors
and enable.

     Ŀ
  B1 1   20 /EN
  A1 2       19 A2
  B0 3       18 B2
  A0 4       17 A3
 GND 5  7411 16 B3
/A=B 6  520  15 VCC
  B7 7       14 A4
  A7 8       13 B4
  B6 9       12 A5
  A6 10      11 B5
     
#
7411521
8-bit inverting identity comparator with enable.

     Ŀ
  B1 1   20 EN
  A1 2       19 A2
  B0 3       18 B2
  A0 4       17 A3
 GND 5  7411 16 B3
/A=B 6  521  15 VCC
  B7 7       14 A4
  A7 8       13 B4
  B6 9       12 A5
  A6 10      11 B5
     
#
7411533
8-bit 3-state inverting transparent latch.

    Ŀ             Ŀ
/Q1 1   24 /OE         /OE LE D /Q 
/Q2 2       23 D1          ͵
/Q3 3       22 D2           1  X  X  Z 
/Q4 4       21 D3           0  0  X  - 
GND 5       20 D4           0  1  0  1 
GND 6 7411  19 VCC          0  1  1  0 
GND 7  533  18 VCC         
GND 8       17 D5
/Q5 9       16 D6
/Q6 10      15 D7
/Q7 11      14 D8
/Q8 12      13 CLK
    
#
7411534
8-bit 3-state inverting D flip-flop.

    Ŀ             Ŀ
/Q1 1   24 /OE         /OECLK D /Q 
/Q2 2       23 D1          ͵
/Q3 3       22 D2           1  X  X  Z 
/Q4 4       21 D3           0  /  0  1 
GND 5       20 D4           0  /  1  0 
GND 6 7411  19 VCC          0 !/  X  - 
GND 7  534  18 VCC         
GND 8       17 D5
/Q5 9       16 D6
/Q6 10      15 D7
/Q7 11      14 D8
/Q8 12      13 CLK
    
#
7411543
8-bit 3-state noninverting registered transceiver.

      Ŀ
/CEBA 1   28 /GBA
   A1 2       27 /LEBA
   A2 3       26 B1
   A3 4       25 B2
   A4 5       24 B3
  GND 6       23 B4
  GND 7  7411 22 VCC
  GND 8  543  21 VCC
  GND 9       20 B5
   A5 10      19 B6
   A6 11      18 B7
   A7 12      17 B8
   A8 13      16 /LEAB
/CEAB 14      15 /GAB
      
#
7411544
8-bit 3-state inverting registered transceiver.

      Ŀ
/CEBA 1   28 /GBA
   A1 2       27 /LEBA
   A2 3       26 B1
   A3 4       25 B2
   A4 5       24 B3
  GND 6       23 B4
  GND 7  7411 22 VCC
  GND 8  544  21 VCC
  GND 9       20 B5
   A5 10      19 B6
   A6 11      18 B7
   A7 12      17 B8
   A8 13      16 /LEAB
/CEAB 14      15 /GAB
      
#
7411590
8-bit 3-state synchronous binary counter with reset and output registers.
Separate clocks for both counter and storage register, ripple carry output.

    Ŀ
 Q1 1   20 Q0
 Q2 2       19 CCLK
 Q3 3       18 /CLKEN
GND 4       17 /RST
GND 5 7411  16 VCC
GND 6  590  15 VCC
GND 7       14 /OE
 Q4 8       13 RCLK
 Q5 9       12 /RCO
 Q6 10      11 Q7
    
#
7411620
8-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

    Ŀ
 A1 1   24 GAB
 A2 2       23 B1
 A3 3       22 B2
 A4 4       21 B3
GND 5       20 B4
GND 6  7411 19 VCC
GND 7  620  18 VCC
GND 8       17 B5
 A5 9       16 B6
 A6 10      15 B7
 A7 11      14 B8
 A8 12      13 /GBA
    
#
7411623
8-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

    Ŀ
 A1 1   24 GAB
 A2 2       23 B1
 A3 3       22 B2
 A4 4       21 B3
GND 5       20 B4
GND 6  7411 19 VCC
GND 7  623  18 VCC
GND 8       17 B5
 A5 9       16 B6
 A6 10      15 B7
 A7 11      14 B8
 A8 12      13 /GBA
    
#
7411640
8-bit 3-state inverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ             Ŀ
 A1 1   24 DIR         /ENDIR A  B 
 A2 2       23 B1          ͵
 A3 3       22 B2           1  X  Z  Z 
 A4 4       21 B3           0  0 /B  Z 
GND 5       20 B4           0  1  Z /A 
GND 6  7411 19 VCC         
GND 7  640  18 VCC
GND 8       17 B5
 A5 9       16 B6
 A6 10      15 B7
 A7 11      14 B8
 A8 12      13 /EN
    
#
7411643
8-bit 3-state inverting/noninverting bus transceiver.
Enable and direction pins control output enables.
A to B transfer is inverted, B to A transfer is not inverted.

    Ŀ
 A1 1   24 DIR
 A2 2       23 B1
 A3 3       22 B2
 A4 4       21 B3
GND 5       20 B4
GND 6  7411 19 VCC
GND 7  643  18 VCC
GND 8       17 B5
 A5 9       16 B6
 A6 10      15 B7
 A7 11      14 B8
 A8 12      13 /OE
    
#
7411646
8-bit 3-state noninverting registered transceiver.

    Ŀ
/OE 1   28 CAB
 A1 2       27 SAB
 A2 3       26 B1
 A3 4       25 B2
 A4 5       24 B3
GND 6       23 B4
GND 7  7411 22 VCC
GND 8  646  21 VCC
GND 9       20 B5
 A5 10      19 B6
 A6 11      18 B7
 A7 12      17 B8
 A8 13      16 CBA
DIR 14      15 SBA
    
#
7411648
8-bit 3-state inverting registered transceiver.

    Ŀ
/OE 1   28 CAB
 A1 2       27 SAB
 A2 3       26 B1
 A3 4       25 B2
 A4 5       24 B3
GND 6       23 B4
GND 7  7411 22 VCC
GND 8  648  21 VCC
GND 9       20 B5
 A5 10      19 B6
 A6 11      18 B7
 A7 12      17 B8
 A8 13      16 CBA
DIR 14      15 SBA
    
#
7411651
8-bit 3-state inverting registered transceiver.

     Ŀ
 GAB 1   28 CAB
  A1 2       27 SAB
  A2 3       26 B1
  A3 4       25 B2
  A4 5       24 B3
 GND 6       23 B4
 GND 7  7411 22 VCC
 GND 8  651  21 VCC
 GND 9       20 B5
  A5 10      19 B6
  A6 11      18 B7
  A7 12      17 B8
  A8 13      16 CBA
/GBA 14      15 SBA
     
#
7411652
8-bit 3-state noninverting registered transceiver.

     Ŀ
 GAB 1   28 CAB
  A1 2       27 SAB
  A2 3       26 B1
  A3 4       25 B2
  A4 5       24 B3
 GND 6       23 B4
 GND 7  7411 22 VCC
 GND 8  652  21 VCC
 GND 9       20 B5
  A5 10      19 B6
  A6 11      18 B7
  A7 12      17 B8
  A8 13      16 CBA
/GBA 14      15 SBA
     
#
7411657
8-bit 3-state noninverting bus transceiver with parity generator/checker.
Enable and direction pins control output enables.

       Ŀ
  P/B8 1   28 /OE
    A0 2       27
    A1 3       26 B0
    A2 4       25 B1
    A3 5       24 B2
   GND 6       23 B3
   GND 7 7411  22 VCC
   GND 8  657  21 VCC
   GND 9       20 B4
    A4 10      19 B5
    A5 11      18 B6
    A6 12      17 B7
    A7 13      16 E//O
/ERROR 14      15 DIR
       
#
7411802
Triple 4-input OR/NOR gates with buffered complementary outputs.

    Ŀ             Ŀ
 1A 1   24 1B           A  B  C  D  Y /Y      Y = A+B+C+D
 1Y 2       23 1C          ͵
/1Y 3       22 1D           0  0  0  0  0  1 
 2Y 4       21 2A           0  0  0  1  1  0 
GND 5       20 2B           0  0  1  X  1  0 
GND 6 7411  19 VCC          0  1  X  X  1  0 
GND 7  802  18 VCC          1  X  X  X  1  0 
GND 8       17 2C          
/2Y 9       16 2D
 3Y 10      15 3A
/3Y 11      14 3B
 3D 12      13 3C
    
#
7411810
Quad 2-input XNOR gates with buffered output.

    Ŀ             Ŀ            _ 
 1A 1   16 1B           A  B /Y       /Y = A$B
/1Y 2       15 2A          ͵
/2Y 3       14 2B           0  0  1 
GND 4  7411 13 VCC          0  1  0 
GND 5   810 12 VCC          1  0  0 
/3Y 6       11 3A           1  1  1 
/4Y 7       10 3B          
 4B 8        9 4A
    
#
7411821
10-bit 3-state D flip-flop.

    Ŀ             Ŀ
 Q1 1   28 /OE         /OECLK D  Q 
 Q2 2       27 D1          ͵
 Q3 3       26 D2           1  X  X  Z 
 Q4 4       25 D3           0  /  0  0 
 Q5 5       24 D4           0  /  1  1 
GND 6       23 D5           0 !/  X  - 
GND 7 7411  22 VCC         
GND 8  821  21 VCC
GND 9       20 D6
 Q6 10      19 D7
 Q7 11      18 D8
 Q8 12      17 D9
 Q9 13      16 D10
Q10 14      15 CLK
    
#
7411825
8-bit 3-state D flip-flop with three output enables, clock enable and reset.

     Ŀ
/OE1 1   28 /OE2
  Q1 2       27 /OE3
  Q2 3       26 D1
  Q3 4       25 D2
  Q4 5       24 D3
 GND 6       23 D4
 GND 7 7411  22 VCC
 GND 8  825  21 VCC
 GND 9       20 D5
  Q5 10      19 D6
  Q6 11      18 D7
  Q7 12      17 D8
  Q8 13      16 /CLKEN
/RST 14      15 CLK
     
#
7411827
10-bit 3-state noninverting buffer/line driver.

    Ŀ
 Y1 1   28 /OE1
 Y2 2       27 A1
 Y3 3       26 A2
 Y4 4       25 A3
 Y5 5       24 A4
GND 6       23 A5
GND 7  7411 22 VCC
GND 8  827  21 VCC
GND 9       20 A6
 Y6 10      19 A7
 Y7 11      18 A8
 Y8 12      17 A9
 Y9 13      16 A10
Y10 14      15 /OE2
    
#
7411828
10-bit 3-state inverting buffer/line driver.

     Ŀ
 /Y1 1   28 /OE1
 /Y2 2       27 A1
 /Y3 3       26 A2
 /Y4 4       25 A3
 /Y5 5       24 A4
 GND 6       23 A5
 GND 7  7411 22 VCC
 GND 8  828  21 VCC
 GND 9       20 A6
 /Y6 10      19 A7
 /Y7 11      18 A8
 /Y8 12      17 A9
 /Y9 13      16 A10
/Y10 14      15 /OE2
     
#
7411862
8-bit 3-state inverting bus transceiver.

    Ŀ
 A1 1   28 /GAB
 A2 2       27 B1
 A3 3       26 B2
 A4 4       25 B3
 A5 5       24 B4
GND 6       23 B5
GND 7  7411 22 VCC
GND 8  862  21 VCC
GND 9       20 B6
 A6 10      19 B7
 A7 11      18 B8
 A8 12      17 B9
 A9 13      16 B10
A10 14      15 /GBA
    
#
7411873
Dual 4-bit 3-state transparent latch with reset.

    Ŀ             Ŀ
1LE 1   28 /1OE        /RST/OE LE D  Q 
1Q1 2       27 /1RST       ͵
1Q2 3       26 1D1           0  0  X  X  0 
1Q3 4       25 1D2           X  1  X  X  Z 
1Q4 5       24 1D3           1  0  0  X  - 
GND 6       23 1D4           1  0  1  0  0 
GND 7 7411  22 VCC           1  0  1  1  1 
GND 8  873  21 VCC         
GND 9       20 2D1
2Q1 10      19 2D2
2Q2 11      18 2D3
2Q3 12      17 2D4
2Q4 13      16 /2RST
2LE 14      15 /2OE
    
#
7411874
Dual 4-bit 3-state D flip-flop with reset.

     Ŀ            Ŀ
1CLK 1   28 /1OE       /RST/OECLK D  Q 
 1Q1 2       27 /1RST      ͵
 1Q2 3       26 1D1          0  1  X  X  Z 
 1Q3 4       25 1D2          X  0  X  X  0 
 1Q4 5       24 1D3          1  0  /  0  0 
 GND 6       23 1D4          1  0  /  1  1 
 GND 7 7411  22 VCC          1  0 !/  X  - 
 GND 8  873  21 VCC        
 GND 9       20 2D1
 2Q1 10      19 2D2
 2Q2 11      18 2D3
 2Q3 12      17 2D4
 2Q4 13      16 /2RST
2CLK 14      15 /2OE
     
#
7411898
10-bit serial-in parallel-out shift register with asynchronous reset.
Gated serial inputs.

    Ŀ
 QC 1   20 QB
 QD 2       19 QA
 QE 3       18 /RST
GND 4       17 A1
GND 5 7411  16 VCC
GND 6  898  15 VCC
GND 7       14 A2
 QF 8       13 CLK
 QG 9       12 QJ
 QH 10      11 QI
    
#
7412
Triple 3-input open-collector NAND gates.

    Ŀ             Ŀ       ___
 1A 1   14 VCC          A  B  C /Y   /Y = ABC
 1B 2       13 1C          ͵
 2A 3       12 /1Y          0  X  X  Z 
 2B 4  7410 11 3C           1  0  X  Z 
 2C 5       10 3B           1  1  0  Z 
/2Y 6        9 3A           1  1  1  0 
GND 7        8 /3Y         
    
#
74121
Monostable multivibrator with Schmitt-trigger inputs.
Programmable output pulse width from 40 ns to 20 seconds.

     Ŀ
  /Q 1   14 VCC
     2       13
/TR1 3   74  12
/TR2 4  121  11 RCext
  TR 5       10 Cext
   Q 6        9 Rint
 GND 7        8
     
#
74122
Retriggerable monostable multivibrator with overriding reset and integrated
10k timing resistor.

     Ŀ
/TR1 1   14 VCC
/TR2 2       13 RCext
 TR1 3   74  12
 TR2 4  122  11 Cext
/RST 5       10
  /Q 6        9 Rint
 GND 7        8 Q
     
#
74123
Dual retriggerable monostable multivibrators with overriding reset.

       Ŀ
  /1TR 1   16 VCC
   1TR 2       15 1RCext
 /1RST 3       14 1Cext
   /1Q 4   74  13 1Q
    2Q 5  123  12 /2Q
 2Cext 6       11 /2RST
2RCext 7       10 2TR
   GND 8        9 /2TR
       
#
74125
Quad 3-state noninverting buffer with active low enables.

     Ŀ            Ŀ
/1OE 1   14 VCC         A /OE Y 
  1A 2       13 /4OE       ͵
  1Y 3   74  12 4A          0  0  0 
/2OE 4  125  11 4Y          1  0  1 
  2A 5       10 /3OE        X  1  Z 
  2Y 6        9 3A         
 GND 7        8 3Y
     
#
74126
Quad 3-state noninverting buffer with active high enables.

    Ŀ             Ŀ
1OE 1   14 VCC          A  OE Y 
 1A 2       13 4OE         ͵
 1Y 3   74  12 4A           X  0  Z 
2OE 4  126  11 4Y           0  1  0 
 2A 5       10 3OE          1  1  1 
 2Y 6        9 3A          
GND 7        8 3Y
    
#
74128
Quad 2-input NOR gates/line drivers.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  1 
/2Y 4  7402 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
7413
Dual 4-input NAND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7413 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
74131
1-of-8 inverting decoder/demultiplexer with address register.

     Ŀ
  S0 1   16 VCC
  S1 2       15 /Y0
  S2 3       14 /Y1
 CLK 4   74  13 /Y2
/EN2 5  131  12 /Y3
 EN1 6       11 /Y4
 /Y7 7       10 /Y5
 GND 8        9 /Y6
     
#
74132
Quad 2-input NAND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4 74132 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
74133
13-input NAND gate.

    Ŀ                 _____________
  A 1   16 VCC        /Y = ABCDEFGHIJKLM
  B 2       15 M
  C 3       14 L
  D 4   74  13 K
  E 5  133  12 J
  F 6       11 I
  G 7       10 H
GND 8        9 /Y
    
#
74136
Quad 2-input open-collector XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4 74136 11 4Y           0  1  Z 
 2B 5       10 3B           1  0  Z 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    
#
74137
1-of-8 inverting decoder/demultiplexer with address latches.

     Ŀ
  S0 1   16 VCC
  S1 2       15 /Y0
  S2 3       14 /Y1
 /LE 4   74  13 /Y2
/EN2 5  137  12 /Y3
 EN1 6       11 /Y4
 /Y7 7       10 /Y5
 GND 8        9 /Y6
     
#
74138
1-of-8 inverting decoder/demultiplexer.

     Ŀ            Ŀ
  S0 1   16 VCC        EN1/EN2/EN3 S2 S1 S0/Y0/Y1.../Y7
  S1 2       15 /Y0        ͵
  S2 3       14 /Y1         0  X    X  X  X  X  1  1  1  1 
/EN3 4   74  13 /Y2         1  1    X  X  X  X  1  1  1  1 
/EN2 5  138  12 /Y3         1  0    1  X  X  X  1  1  1  1 
 EN1 6       11 /Y4         1  0    0  0  0  0  0  1  1  1 
 /Y7 7       10 /Y5         1  0    0  0  0  1  1  0  1  1 
 GND 8        9 /Y6         1  0    0  .  .  .  1  1  .  1 
                  1  0    0  1  1  1  1  1  1  0 
                             
#
74139
Dual 1-of-4 inverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0/Y0/Y1/Y2/Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  1  1  1  1 
/1Y0 4   74  13 2S1         0  0  0  0  1  1  1 
/1Y1 5  139  12 /2Y0        0  0  1  1  0  1  1 
/1Y2 6       11 /2Y1        0  1  0  1  1  0  1 
/1Y3 7       10 /2Y2        0  1  1  1  1  1  0 
 GND 8        9 /2Y3       
     
#
7414
Hex inverters with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4  7414 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
74140
Dual 4-input NAND gates/50 line drivers.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3   74  12 2C           0  X  X  X  1 
 1C 4  140  11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
74141
1-of-10 inverting decoder/demultiplexer.

    Ŀ             Ŀ
/Y8 1   16 /Y0          S3 S2 S1 S0/Y0/Y1.../Y9
/Y9 2       15 /Y1         ͵
 S0 3       14 /Y5          0  0  0  0  0  1  1  1 
 S3 4   74  13 /Y4          0  0  0  1  1  0  1  1 
VCC 5  141  12 GND          .  .  .  .  1  1  .  1 
 S1 6       11 /Y6          1  0  0  1  1  1  1  0 
 S2 7       10 /Y7          1  0  1  X  1  1  1  1 
/Y2 8        9 /Y3          1  1  X  X  1  1  1  1 
                 
#
74145
1-of-10 open-collector inverting decoder/demultiplexer.

    Ŀ             Ŀ
/Y0 1   16 VCC          S3 S2 S1 S0/Y0/Y1.../Y9
/Y1 2       15 S0          ͵
/Y2 3       14 S1           0  0  0  0  0  Z  Z  Z 
/Y3 4   74  13 S2           0  0  0  1  Z  0  Z  Z 
/Y4 5  145  12 S3           .  .  .  .  Z  Z  .  Z 
/Y5 6       11 /Y9          1  0  0  1  Z  Z  Z  0 
/Y6 7       10 /Y8          1  0  1  X  Z  Z  Z  Z 
GND 8        9 /Y7          1  1  X  X  Z  Z  Z  Z 
                 
#
74147
10-to-4 line inverting priority encoder.

    Ŀ
/A4 1   16 VCC
/A5 2       15
/A6 3       14 Y3
/A7 4   74  13 /A3
/A8 5  147  12 /A2
 Y2 6       11 /A1
 Y1 7       10 /A9
GND 8        9 Y0
    
#
74148
8-to-3 line inverting priority encoder with cascade inputs.

    Ŀ
/A4 1   16 VCC
/A5 2       15 /EO
/A6 3       14 /GS
/A7 4   74  13 /A3
/EI 5  148  12 /A2
 Y2 6       11 /A1
 Y1 7       10 /A0
GND 8        9 Y0
    
#
7415
Triple 3-input open-collector AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  C  Y    Y = ABC
 1B 2       13 1C          ͵
 2A 3       12 1Y           0  X  X  0 
 2B 4  7415 11 3C           1  0  X  0 
 2C 5       10 3B           1  1  0  0 
 2Y 6        9 3A           1  1  1  Z 
GND 7        8 3Y          
    
#
74150
16-to-1 line inverting data selector/multiplexer.

    Ŀ
 D7 1   24 VCC
 D6 2       23 D8
 D5 3       22 D9
 D4 4       21 D10
 D3 5       20 D11
 D2 6   74  19 D12
 D1 7  150  18 D13
 D0 8       17 D14
/EN 9       16 D15
 /Y 10      15 S0
 S3 11      14 S1
GND 12      13 S2
    
#
74151
8-to-1 line data selector/multiplexer with complementary outputs.

    Ŀ
 D3 1   16 VCC
 D2 2       15 D4
 D1 3       14 D5
 D0 4   74  13 D6
  Y 5  151  12 D7
 /Y 6       11 S0
/EN 7       10 S1
GND 8        9 S2
    
#
74152
8-to-1 line inverting data selector/multiplexer.

    Ŀ
 A4 1   14 VCC
 A3 2       13 A5
 A2 3   74  12 A6
 A1 4  152  11 A7
 A0 5       10 S0
 /Y 6        9 S1
GND 7        8 S1
    
#
74153
8-to-2 line noninverting data selector/multiplexer with separate enables.

     Ŀ
/1EN 1   16 VCC
  S1 2       15 /2EN
 1A3 3       14 S0
 1A2 4   74  13 2A3
 1A1 5  153  12 2A2
 1A0 6       11 2A1
  1Y 7       10 2A0
 GND 8        9 2Y
     
#
74154
1-of-16 inverting decoder/demultiplexer.

     Ŀ
 /Y0 1   24 VCC
 /Y1 2       23 S0
 /Y2 3       22 S1
 /Y3 4       21 S2
 /Y4 5       20 S3
 /Y5 6   74  19 /EN2
 /Y6 7  154  18 /EN1
 /Y7 8       17 /Y15
 /Y8 9       16 /Y14
 /Y9 10      15 /Y13
/Y10 11      14 /Y12
 GND 12      13 /Y11
     
#
74155
2-of-8 inverting decoder/demultiplexer with separate enables.

      Ŀ
 1EN1 1   16 VCC
/1EN2 2       15 /2EN1
   S1 3       14 /2EN2
 /1Y3 4   74  13 S0
 /1Y2 5  155  12 /2Y3
 /1Y1 6       11 /2Y2
 /1Y0 7       10 /2Y1
  GND 8        9 /2Y0
      
#
74156
2-of-8 open-collector inverting decoder/demultiplexer with separate enables.

      Ŀ
 1EN1 1   16 VCC
/1EN2 2       15 /2EN1
   S1 3       14 /2EN2
 /1Y3 4   74  13 S0
 /1Y2 5  156  12 /2Y3
 /1Y1 6       11 /2Y2
 /1Y0 7       10 /2Y1
  GND 8        9 /2Y0
      
#
74157
4-of-8 noninverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  157  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    
#
74158
4-of-8 inverting decoder/demultiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
/1Y 4   74  13 4A1
2A0 5  158  12 /4Y
2A1 6       11 3A0
/2Y 7       10 3A1
GND 8        9 /3Y
    
#
74159
1-of-16 open-collector inverting decoder/demultiplexer.

     Ŀ
 /Y0 1   24 VCC
 /Y1 2       23 S0
 /Y2 3       22 S1
 /Y3 4       21 S2
 /Y4 5       20 S3
 /Y5 6   74  19 /EN2
 /Y6 7  159  18 /EN1
 /Y7 8       17 /Y15
 /Y8 9       16 /Y14
 /Y9 10      15 /Y13
/Y10 11      14 /Y12
 GND 12      13 /Y11
     
#
7416
Hex open-collector high-voltage inverters.
Maximum output voltage is 15V.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  Z 
/2Y 4  7416 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
74160, 40160
4-bit synchronous decade counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  160  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     
#
74161, 40161
4-bit synchronous binary counter with load, asynchronous reset, and ripple
carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  161  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     
#
74162, 40162
4-bit synchronous decade counter with load, reset, and ripple carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  162  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     
#
74162240
Quad 4-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/1OE 1   48 /2OE
/1Y1 2       47 1A1
/1Y2 3       46 1A2
 GND 4       45 GND
/1Y3 5       44 1A3
/1Y4 6       43 1A4
 VCC 7       42 VCC
/2Y1 8       41 2A1
/2Y2 9       40 2A2
 GND 10      39 GND
/2Y3 11      38 2A3
/2Y4 12 7416 37 2A4
/3Y1 13 2240 36 3A1
/3Y2 14      35 3A2
 GND 15      34 GND
/3Y3 16      33 3A3
/3Y4 17      32 3A4
 VCC 18      31 VCC
/4Y1 19      30 4A1
/4Y2 20      29 4A2
 GND 21      28 GND
/4Y3 22      27 4A3
/4Y4 23      26 4A4
/4OE 24      25 /3OE
     
#
74162244
Quad 4-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/1OE 1   48 /2OE
 1Y1 2       47 1A1
 1Y2 3       46 1A2
 GND 4       45 GND
 1Y3 5       44 1A3
 1Y4 6       43 1A4
 VCC 7       42 VCC
 2Y1 8       41 2A1
 2Y2 9       40 2A2
 GND 10      39 GND
 2Y3 11      38 2A3
 2Y4 12 7416 37 2A4
 3Y1 13 2241 36 3A1
 3Y2 14      35 3A2
 GND 15      34 GND
 3Y3 16      33 3A3
 3Y4 17      32 3A4
 VCC 18      31 VCC
 4Y1 19      30 4A1
 4Y2 20      29 4A2
 GND 21      28 GND
 4Y3 22      27 4A3
 4Y4 23      26 4A4
/4OE 24      25 /3OE
     
#
74162260
12-bit to 24-bit multiplexed D-type latch/MOS driver.

     Ŀ
/OEA 1   56 /O2B
LE1B 2       55 LA2B
 2B3 3       54 2B4
 GND 4       53 GND
 2B2 5       52 2B5
 2B1 6       51 2B6
 VCC 7       50 VCC
  A1 8       49 2B7
  A2 9       48 2B8
  A3 10      47 2B9
 GND 11      46 GND
  A4 12      45 2B10
  A5 13      44 2B11
  A6 14 7416 43 2B12
  A7 15 2260 42 1B12
  A8 16      41 1B11
  A9 17      40 1B10
 GND 18      39 GND
 A10 19      38 1B9
 A11 20      37 1B8
 A12 21      36 1B7
 VCC 22      35 VCC
 1B1 23      34 1B6
 1B2 24      33 1B5
 GND 25      32 GND
 1B3 26      31 1B4
LE2B 27      30 LA1B
   S 28      29 /O1B
     
#
7416240
Quad 4-bit 3-state inverting buffer/line driver.

     Ŀ
/1OE 1   48 /2OE
/1Y1 2       47 1A1
/1Y2 3       46 1A2
 GND 4       45 GND
/1Y3 5       44 1A3
/1Y4 6       43 1A4
 VCC 7       42 VCC
/2Y1 8       41 2A1
/2Y2 9       40 2A2
 GND 10      39 GND
/2Y3 11      38 2A3
/2Y4 12 7416 37 2A4
/3Y1 13  240 36 3A1
/3Y2 14      35 3A2
 GND 15      34 GND
/3Y3 16      33 3A3
/3Y4 17      32 3A4
 VCC 18      31 VCC
/4Y1 19      30 4A1
/4Y2 20      29 4A2
 GND 21      28 GND
/4Y3 22      27 4A3
/4Y4 23      26 4A4
/4OE 24      25 /3OE
     
#
7416241
Quad 4-bit 3-state noninverting buffer/line driver.
Two active low, two active high output enables.

     Ŀ
/1OE 1   48 2OE
 1Y1 2       47 1A1
 1Y2 3       46 1A2
 GND 4       45 GND
 1Y3 5       44 1A3
 1Y4 6       43 1A4
 VCC 7       42 VCC
 2Y1 8       41 2A1
 2Y2 9       40 2A2
 GND 10      39 GND
 2Y3 11      38 2A3
 2Y4 12 7416 37 2A4
 3Y1 13  241 36 3A1
 3Y2 14      35 3A2
 GND 15      34 GND
 3Y3 16      33 3A3
 3Y4 17      32 3A4
 VCC 18      31 VCC
 4Y1 19      30 4A1
 4Y2 20      29 4A2
 GND 21      28 GND
 4Y3 22      27 4A3
 4Y4 23      26 4A4
/4OE 24      25 3OE
     
#
7416244
Quad 4-bit 3-state noninverting buffer/line driver.

     Ŀ
/1OE 1   48 /2OE
 1Y1 2       47 1A1
 1Y2 3       46 1A2
 GND 4       45 GND
 1Y3 5       44 1A3
 1Y4 6       43 1A4
 VCC 7       42 VCC
 2Y1 8       41 2A1
 2Y2 9       40 2A2
 GND 10      39 GND
 2Y3 11      38 2A3
 2Y4 12 7416 37 2A4
 3Y1 13  244 36 3A1
 3Y2 14      35 3A2
 GND 15      34 GND
 3Y3 16      33 3A3
 3Y4 17      32 3A4
 VCC 18      31 VCC
 4Y1 19      30 4A1
 4Y2 20      29 4A2
 GND 21      28 GND
 4Y3 22      27 4A3
 4Y4 23      26 4A4
/4OE 24      25 /3OE
     
#
7416245
Dual 8-bit 3-state noninverting bus transceiver.

     Ŀ            Ŀ
1DIR 1   48 /1EN       /ENDIR A  B 
 1B1 2       47 1A1        ͵
 1B2 3       46 1A2         1  X  Z  Z 
 GND 4       45 GND         0  0  B  Z 
 1B3 5       44 1A3         0  1  Z  A 
 1B4 6       43 1A4        
 VCC 7       42 VCC
 1B5 8       41 1A5
 1B6 9       40 1A6
 GND 10      39 GND
 1B7 11      38 1A7
 1B8 12 7416 37 1A8
 2B1 13  245 36 2A1
 2B2 14      35 2A2
 GND 15      34 GND
 2B3 16      33 2A3
 2B4 17      32 2A4
 VCC 18      31 VCC
 2B5 19      30 2A5
 2B6 20      29 2A6
 GND 21      28 GND
 2B7 22      27 2A7
 2B8 23      26 2A8
2DIR 24      25 /2EN
     
#
7416260
12-bit to 24-bit multiplexed D-type latch.

     Ŀ
/OEA 1   56 /O2B
LE1B 2       55 LA2B
 2B3 3       54 2B4
 GND 4       53 GND
 2B2 5       52 2B5
 2B1 6       51 2B6
 VCC 7       50 VCC
  A1 8       49 2B7
  A2 9       48 2B8
  A3 10      47 2B9
 GND 11      46 GND
  A4 12      45 2B10
  A5 13      44 2B11
  A6 14 7416 43 2B12
  A7 15  260 42 1B12
  A8 16      41 1B11
  A9 17      40 1B10
 GND 18      39 GND
 A10 19      38 1B9
 A11 20      37 1B8
 A12 21      36 1B7
 VCC 22      35 VCC
 1B1 23      34 1B6
 1B2 24      33 1B5
 GND 25      32 GND
 1B3 26      31 1B4
LE2B 27      30 LA1B
 SEL 28      29 /O1B
     
#
74163, 40163
4-bit synchronous binary counter with load, reset, and ripple carry output.

     Ŀ
/RST 1   16 VCC
 CLK 2       15 RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  163  12 Q2
  P3 6       11 Q3
 ENP 7       10 ENT
 GND 8        9 /LOAD
     
#
7416373
Dual 8-bit 3-state transparent latches.

     Ŀ            Ŀ
/1OE 1   48 1LE        /OE LE D  Q 
 1Q1 2       47 1D1        ͵
 1Q2 3       46 1D2         1  X  X  Z 
 GND 4       45 GND         0  0  X  - 
 1Q3 5       44 1D3         0  1  0  0 
 1Q4 6       43 1D4         0  1  1  1 
 VCC 7       42 VCC        
 1Q5 8       41 1D5
 1Q6 9       40 1D6
 GND 10      39 GND
 1Q7 11      38 1D7
 1Q8 12 7416 37 1D8
 2Q1 13 373  36 2D1
 2Q2 14      35 2D2
 GND 15      34 GND
 2Q3 16      33 2D3
 2Q4 17      32 2D4
 VCC 18      31 VCC
 2Q5 19      30 2D5
 2Q6 20      29 2D6
 GND 21      28 GND
 2Q7 22      27 2D7
 2Q8 23      26 2D8
/2OE 24      25 2LE
     
#
7416374
Dual 8-bit 3-state D flip-flops.

     Ŀ            Ŀ
/1OE 1   48 1CLK       /OECLK D  Q 
 1Q1 2       47 1D1        ͵
 1Q2 3       46 1D2         1  X  X  Z 
 GND 4       45 GND         0  /  0  0 
 1Q3 5       44 1D3         0  /  1  1 
 1Q4 6       43 1D4         0 !/  X  - 
 VCC 7       42 VCC        
 1Q5 8       41 1D5
 1Q6 9       40 1D6
 GND 10      39 GND
 1Q7 11      38 1D7
 1Q8 12 7416 37 1D8
 2Q1 13 374  36 2D1
 2Q2 14      35 2D2
 GND 15      34 GND
 2Q3 16      33 2D3
 2Q4 17      32 2D4
 VCC 18      31 VCC
 2Q5 19      30 2D5
 2Q6 20      29 2D6
 GND 21      28 GND
 2Q7 22      27 2D7
 2Q8 23      26 2D8
/2OE 24      25 2CLK
     
#
74164
8-bit serial-in parallel-out shift register with asynchronous reset.
Gated serial inputs.

    Ŀ
 A1 1   14 VCC
 A2 2       13 QH
 QA 3   74  12 QGH
 QB 4  164  11 QF
 QC 5       10 QE
 QD 6        9 /RST
GND 7        8 CLK
    
#
7416470
Dual 8-bit 3-state noninverting registered transceiver.

     Ŀ
/1OA 1   56 /1OB
1CKA 2       55 1CKB
/1CA 3       54 /1CB
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  470 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
/2CA 26      31 /2CB
2CKA 27      30 2CKB
/2OA 28      29 /2OB
     
#
7416472
Dual 9-bit 3-state noninverting latched transceiver.

     Ŀ
/1OA 1   56 /1OB
/1LA 2       55 /1LB
 1A1 3       54 1B1
 GND 4       53 GND
 1A2 5       52 1B2
 1A3 6       51 1B3
 VCC 7       50 VCC
 1A4 8       49 1B4
 1A5 9       48 1B5
 1A6 10      47 1B6
 GND 11      46 GND
 1A7 12      45 1B7
 1A8 13      44 1B8
 1A9 14 7416 43 1B9
 2A1 15  472 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
 2A9 26      31 2B9
/2LA 27      30 /2LB
/2OA 28      29 /2OB
     
#
7416474
Dual 9-bit 3-state noninverting registered transceiver.

     Ŀ
/1OB 1   56 /1OA
1CAB 2       55 1CBA
 1A1 3       54 1B1
 GND 4       53 GND
 1A2 5       52 1B2
 1A3 6       51 1B3
 VCC 7       50 VCC
 1A4 8       49 1B4
 1A5 9       48 1B5
 1A6 10      47 1B6
 GND 11      46 GND
 1A7 12      45 1B7
 1A8 13      44 1B8
 1A9 14 7416 43 1B9
 2A1 15  474 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
 2A9 26      31 2B9
2CAB 27      30 2CBA
/2OB 28      29 /2OA
     
#
7416475
Dual 9-bit 3-state noninverting registered transceiver.

     Ŀ
/1OA 1   56 /1OB
1CKA 2       55 1CKB
 1A1 3       54 1B1
 GND 4       53 GND
 1A2 5       52 1B2
 1A3 6       51 1B3
 VCC 7       50 VCC
 1A4 8       49 1B4
 1A5 9       48 1B5
 1A6 10      47 1B6
 GND 11      46 GND
 1A7 12      45 1B7
 1A8 13      44 1B8
 1A9 14 7416 43 1B9
 2A1 15  475 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
 2A9 26      31 2B9
2CKA 27      30 2CKB
/2OA 28      29 /2OB
     
#
74165
8-bit parallel-in serial-out shift register with asynchronous parallel load
and two gated clock inputs.

       Ŀ
SH//LD 1   16 VCC
  CLK1 2       15 CLK2
    P3 3       14 P4
    P2 4   74  13 P5
    P1 5  165  12 P6
    P0 6       11 P7
   /QH 7       10 D
   GND 8        9 QH
       
#
7416500
18-bit 3-state noninverting latched/registered transceiver.

     Ŀ
OEAB 1   56 GND
LEAB 2       55 /CAB
  A1 3       54 B1
 GND 4       53 GND
  A2 5       52 B2
  A3 6       51 B3
 VCC 7       50 VCC
  A4 8       49 B4
  A5 9       48 B5
  A6 10      47 B6
 GND 11      46 GND
  A7 12      45 B7
  A8 13      44 B8
  A9 14 7416 43 B9
 A10 15  500 42 B10
 A11 16      41 B11
 A12 17      40 B12
 GND 18      39 GND
 A13 19      38 B13
 A14 20      37 B14
 A15 21      36 B15
 VCC 22      35 VCC
 A16 23      34 B16
 A17 24      33 B17
 GND 25      32 GND
 A18 26      31 B18
/OBA 27      30 /CBA
LEBA 28      29 GND
     
#
7416501
18-bit 3-state noninverting latched/registered transceiver.

     Ŀ
OEAB 1   56 GND
LEAB 2       55 CLKAB
  A1 3       54 B1
 GND 4       53 GND
  A2 5       52 B2
  A3 6       51 B3
 VCC 7       50 VCC
  A4 8       49 B4
  A5 9       48 B5
  A6 10      47 B6
 GND 11      46 GND
  A7 12      45 B7
  A8 13      44 B8
  A9 14 7416 43 B9
 A10 15  501 42 B10
 A11 16      41 B11
 A12 17      40 B12
 GND 18      39 GND
 A13 19      38 B13
 A14 20      37 B14
 A15 21      36 B15
 VCC 22      35 VCC
 A16 23      34 B16
 A17 24      33 B17
 GND 25      32 GND
 A18 26      31 B18
/OEA 27      30 CLKBA
LEBA 28      29 GND
     
#
7416540
Quad 4-bit 3-state inverting buffer/line drivers.

     Ŀ
/1O1 1   48 /1O2
/1Y1 2       47 1A1
/1Y2 3       46 1A2
 GND 4       45 GND
/1Y3 5       44 1A3
/1Y4 6       43 1A4
 VCC 7       42 VCC
/1Y5 8       41 1A5
/1Y6 9       40 1A6
 GND 10      39 GND
/1Y7 11      38 1A7
/1Y8 12 7416 37 1A8
/2Y1 13  540 36 2A1
/2Y2 14      35 2A2
 GND 15      34 GND
/2Y3 16      33 2A3
/2Y4 17      32 2A4
 VCC 18      31 VCC
/2Y5 19      30 2A5
/2Y6 20      29 2A6
 GND 21      28 GND
/2Y7 22      27 2A7
/2Y8 23      26 2A8
/2O1 24      25 /2O2
     
#
7416541
Quad 4-bit 3-state noninverting buffer/line driver.

     Ŀ
/1O1 1   48 /1O2
 1Y1 2       47 1A1
 1Y2 3       46 1A2
 GND 4       45 GND
 1Y3 5       44 1A3
 1Y4 6       43 1A4
 VCC 7       42 VCC
 1Y5 8       41 1A5
 1Y6 9       40 1A6
 GND 10      39 GND
 1Y7 11      38 1A7
 1Y8 12 7416 37 1A8
 2Y1 13  541 36 2A1
 2Y2 14      35 2A2
 GND 15      34 GND
 2Y3 16      33 2A3
 2Y4 17      32 2A4
 VCC 18      31 VCC
 2Y5 19      30 2A5
 2Y6 20      29 2A6
 GND 21      28 GND
 2Y7 22      27 2A7
 2Y8 23      26 2A8
/2O1 24      25 /2O2
     
#
7416543
Dual 8-bit 3-state noninverting registered transceiver.

     Ŀ
/1OA 1   56 /1OB
/1LA 2       55 /1LB
/1CA 3       54 /1CB
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  543 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
/2CA 26      31 /2CB
/2LA 27      30 /2LB
/2OA 28      29 /2OB
     
#
7416544
Dual 8-bit 3-state noninverting registered transceiver.

     Ŀ
/1OA 1   56 /1OB
/1LA 2       55 /1LB
/1CA 3       54 /1CB
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  544 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
/2CA 26      31 /2CB
/2LA 27      30 /2LB
/2OA 28      29 /2OB
     
#
74166
8-bit parallel-in serial-out shift register with asynchronous reset.

     Ŀ
  SA 1   16 VCC
   A 2       15 SH//LD
   B 3       14 H
   C 4   74  13 QH
   D 5  166  12 G
CLK1 6       11 F
CLK2 7       10 E
 GND 8        9 /RST
     
#
7416600
18-bit 3-state noninverting latched/registered transceiver.

     Ŀ
/OAB 1   56 /CEB
LEAB 2       55 /CAB
  A1 3       54 B1
 GND 4       53 GND
  A2 5       52 B2
  A3 6       51 B3
 VCC 7       50 VCC
  A4 8       49 B4
  A5 9       48 B5
  A6 10      47 B6
 GND 11      46 GND
  A7 12      45 B7
  A8 13      44 B8
  A9 14 7416 43 B9
 A10 15  600 42 B10
 A11 16      41 B11
 A12 17      40 B12
 GND 18      39 GND
 A13 19      38 B13
 A14 20      37 B14
 A15 21      36 B15
 VCC 22      35 VCC
 A16 23      34 B16
 A17 24      33 B17
 GND 25      32 GND
A18A 26      31 B18
/OBA 27      30 /CBA
LEBA 28      29 /CEA
     
#
7416601
18-bit 3-state noninverting latched/registered transceiver.

     Ŀ
/OAB 1   56 /CEB
LEAB 2       55 /CAB
  A1 3       54 B1
 GND 4       53 GND
  A2 5       52 B2
  A3 6       51 B3
 VCC 7       50 VCC
  A4 8       49 B4
  A5 9       48 B5
  A6 10      47 B6
 GND 11      46 GND
  A7 12      45 B7
  A8 13      44 B8
  A9 14 7416 43 B9
 A10 15  600 42 B10
 A11 16      41 B11
 A12 17      40 B12
 GND 18      39 GND
 A13 19      38 B13
 A14 20      37 B14
 A15 21      36 B15
 VCC 22      35 VCC
 A16 23      34 B16
 A17 24      33 B17
 GND 25      32 GND
A18A 26      31 B18
/OBA 27      30 /CBA
LEBA 28      29 /CEA
     
#
7416620
Dual 8-bit 3-state inverting bus transceiver.

     Ŀ
1GAB 1   48 /1GA
 1B1 2       47 1A1
 1B2 3       46 1A2
 GND 4       45 GND
 1B3 5       44 1A3
 1B4 6       43 1A4
 VCC 7       42 VCC
 1B5 8       41 1A5
 1B6 9       40 1A6
 GND 10      39 GND
 1B7 11      38 1A7
 1B8 12 7416 37 1A8
 2B1 13  620 36 2A1
 2B2 14      35 2A2
 GND 15      34 GND
 2B3 16      33 2A3
 2B4 17      32 2A4
 VCC 18      31 VCC
 2B5 19      30 2A5
 2B6 20      29 2A6
 GND 21      28 GND
 2B7 22      27 2A7
 2B8 23      26 2A8
2GAB 24      25 /2GA
     
#
7416623
Dual 8-bit 3-state noninverting bus transceiver.

     Ŀ
1OAB 1   48 /1OA
 1B1 2       47 1A1
 1B2 3       46 1A2
 GND 4       45 GND
 1B3 5       44 1A3
 1B4 6       43 1A4
 VCC 7       42 VCC
 1B5 8       41 1A5
 1B6 9       40 1A6
 GND 10      39 GND
 1B7 11      38 1A7
 1B8 12 7416 37 1A8
 2B1 13  623 36 2A1
 2B2 14      35 2A2
 GND 15      34 GND
 2B3 16      33 2A3
 2B4 17      32 2A4
 VCC 18      31 VCC
 2B5 19      30 2A5
 2B6 20      29 2A6
 GND 21      28 GND
 2B7 22      27 2A7
 2B8 23      26 2A8
2OAB 24      25 /2OA
     
#
7416640
Dual 8-bit 3-state noninverting bus transceiver.

     Ŀ            Ŀ
1DIR 1   48 /1EN       /ENDIR A  B 
 1B1 2       47 1A1        ͵
 1B2 3       46 1A2         1  X  Z  Z 
 GND 4       45 GND         0  0 /B  Z 
 1B3 5       44 1A3         0  1  Z /A 
 1B4 6       43 1A4        
 VCC 7       42 VCC
 1B5 8       41 1A5
 1B6 9       40 1A6
 GND 10      39 GND
 1B7 11      38 1A7
 1B8 12 7416 37 1A8
 2B1 13  640 36 2A1
 2B2 14      35 2A2
 GND 15      34 GND
 2B3 16      33 2A3
 2B4 17      32 2A4
 VCC 18      31 VCC
 2B5 19      30 2A5
 2B6 20      29 2A6
 GND 21      28 GND
 2B7 22      27 2A7
 2B8 23      26 2A8
2DIR 24      25 /2EN
     
#
7416646
Dual 8-bit 3-state noninverting registered transceiver.

     Ŀ
1DIR 1   56 /1EN
1CAB 2       55 1CBA
1SAB 3       54 1SBA
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  646 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
2SAB 26      31 2SBA
2CAB 27      30 2CBA
2DIR 28      29 /2EN
     
#
7416648
Dual 8-bit 3-state inverting registered transceiver.

     Ŀ
1DIR 1   56 /1EN
1CAB 2       55 1CBA
1SAB 3       54 1SBA
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  648 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
2SAB 26      31 2SBA
2CAB 27      30 2CBA
2DIR 28      29 /2EN
     
#
7416651
Dual 8-bit 3-state inverting registered transceiver.

     Ŀ
/1OA 1   56 /1OB
1CKA 2       55 1CKB
1SAB 3       54 1SBA
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  651 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
2SAB 26      31 2SBA
2CKA 27      30 2CKB
/2OA 28      29 /2OB
     
#
7416652
Dual 8-bit 3-state noninverting registered transceiver.

     Ŀ
1GAB 1   56 /1GB
1CAB 2       55 1CBA
1SAB 3       54 1SBA
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  652 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
2SAB 26      31 2SBA
2CAB 27      30 2CBA
2GAB 28      29 /2GB
     
#
7416657
Dual 8-bit 3-state noninverting bus transceiver with parity generator/checker.

      Ŀ
 /1OE 1   56 1DIR
      2       55 1O//E
/1ERR 3       54 1PAR
  GND 4       53 GND
  1A0 5       52 1B0
  1A1 6       51 1B1
  VCC 7       50 VCC
  1A2 8       49 1B2
  1A3 9       48 1B3
  1A4 10      47 1B4
  GND 11      46 GND
  1A5 12      45 1B5
  1A6 13      44 1B6
  1A7 14 7416 43 1B7
  2A0 15  657 42 2B0
  2A1 16      41 2B1
  2A2 17      40 2B2
  GND 18      39 GND
  2A3 19      38 2B3
  2A4 20      37 2B4
  2A5 21      36 2B5
  VCC 22      35 VCC
  2A6 23      34 2B6
  2A7 24      33 2B7
  GND 25      32 GND
/2ERR 26      31 2PAR
      27      30 2O//E
 /2OE 28      29 2DIR
      
#
74167
4-bit synchronous decade rate multiplier.
Can perform fixed-rate or variable-rate frequency division.
Output frequency is equal to input frequency multiplied by the rate input M
and divided by 10.

      Ŀ
      1   16 VCC
   B2 2       15 B1
   B3 3       14 B0
SET-9 4   74  13 RST
    Z 5  167  12 U/CAS
    Y 6       11 ENin
ENout 7       10 STRB
  GND 8        9 CLK
      
#
74168
4-bit synchronous decade up/down counter with load and ripple carry output.

     Ŀ
U//D 1   16 VCC
 CLK 2       15 /RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  168  12 Q2
  P3 6       11 Q3
/ENP 7       10 /ENT
 GND 8        9 /LOAD
     
#
7416821
Dual 10-bit 3-state D flip-flops.

     Ŀ            Ŀ
/1OE 1   56 1CLK       /OECLK D  Q 
 1Q1 2       55 1D1        ͵
 1Q2 3       54 1D2         1  X  X  Z 
 GND 4       53 GND         0  /  0  0 
 1Q3 5       52 1D3         0  /  1  1 
 1Q4 6       51 1D4         0 !/  X  - 
 VCC 7       50 VCC        
 1Q5 8       49 1D5
 1Q6 9       48 1D6
 1Q7 10      47 1D7
 GND 11      46 GND
 1Q8 12      45 1D8
 1Q9 13      44 1D9
1Q10 14 7416 43 1D10
 2Q1 15 821  42 2D1
 2Q2 16      41 2D2
 2Q3 17      40 2D3
 GND 18      39 GND
 2Q4 19      38 2D4
 2Q5 20      37 2D5
 2Q6 21      36 2D6
 VCC 22      35 VCC
 2Q7 23      34 2D7
 2Q8 24      33 2D8
 GND 25      32 GND
 2Q9 26      31 2D9
2Q10 27      30 2D10
/2OE 28      29 2CLK
     
#
7416823
Dual 9-bit 3-state D flip-flops with clock enable and reset.

      Ŀ
/1RST 1   56 1CLK
 /1OE 2       55 /1CLKEN
  1Q1 3       54 1D1
  GND 4       53 GND
  1Q2 5       52 1D2
  1Q3 6       51 1D3
  VCC 7       50 VCC
  1Q4 8       49 1D4
  1Q5 9       48 1D5
  1Q6 10      47 1D6
  GND 11      46 GND
  1Q7 12      45 1D7
  1Q8 13      44 1D8
  1Q9 14 7416 43 1D9
  2Q1 15 823  42 2D1
  2Q2 16      41 2D2
  2Q3 17      40 2D3
  GND 18      39 GND
  2Q4 19      38 2D4
  2Q5 20      37 2D5
  2Q6 21      36 2D6
  VCC 22      35 VCC
  2Q7 23      34 2D7
  2Q8 24      33 2D8
  GND 25      32 GND
  2Q9 26      31 2D9
 /2OE 27      30 /2CLKEN
/2RST 28      29 2CLK
      
#
7416825
Dual 9-bit 3-state noninverting buffer/line driver.

      Ŀ
/1OE1 1   56 /1OE2
  1Y1 2       55 1A1
  1Y2 3       54 1A2
  GND 4       53 GND
  1Y3 5       52 1A3
  1Y4 6       51 1A4
  VCC 7       50 VCC
  1Y5 8       49 1A5
  1Y6 9       48 1A6
  1Y7 10      47 1A7
  GND 11      46 GND
  1Y8 12      45 1A8
  1Y9 13      44 1A9
  GND 14 7416 43 GND
  GND 15  825 42 GND
  2Y1 16      41 2A1
  2Y2 17      40 2A2
  GND 18      39 GND
  2Y3 19      38 2A3
  2Y4 20      37 2A4
  2Y5 21      36 VCC
  VCC 22      35 2A5
  2Y6 23      34 2A6
  2Y7 24      33 2A7
  GND 25      32 GND
  2Y8 26      31 2A8
  2Y9 27      30 2A9
/2OE1 28      29 /2OE2
      
#
7416827
Dual 10-bit 3-state noninverting buffer/line driver.

     Ŀ
/1O1 1   56 /1O2
 1Y1 2       55 1A1
 1Y2 3       54 1A2
 GND 4       53 GND
 1Y3 5       52 1A3
 1Y4 6       51 1A4
 VCC 7       50 VCC
 1Y5 8       49 1A5
 1Y6 9       48 1A6
 1Y7 10      47 1A7
 GND 11      46 GND
 1Y8 12      45 1A8
 1Y9 13      44 1A9
1Y10 14 7416 43 1A10
 2Y1 15  827 42 2A1
 2Y2 16      41 2A2
 2Y3 17      40 2A3
 GND 18      39 GND
 2Y4 19      38 2A4
 2Y5 20      37 2A5
 2Y6 21      36 2A6
 VCC 22      35 VCC
 2Y7 23      34 2A7
 2Y8 24      33 2A8
 GND 25      32 GND
 2Y9 26      31 2A9
2Y10 27      30 2A10
/2O1 28      29 /2O2
     
#
7416828
Dual 10-bit 3-state inverting buffer/line driver.

     Ŀ
/1O1 1   56 /1O2
/1Y1 2       55 1A1
/1Y2 3       54 1A2
 GND 4       53 GND
/1Y3 5       52 1A3
/1Y4 6       51 1A4
 VCC 7       50 VCC
/1Y5 8       49 1A5
/1Y6 9       48 1A6
/1Y7 10      47 1A7
 GND 11      46 GND
/1Y8 12      45 1A8
/1Y9 13      44 1A9
1Y10 14 7416 43 1A10
/2Y1 15  828 42 2A1
/2Y2 16      41 2A2
/2Y3 17      40 2A3
 GND 18      39 GND
/2Y4 19      38 2A4
/2Y5 20      37 2A5
/2Y6 21      36 2A6
 VCC 22      35 VCC
/2Y7 23      34 2A7
/2Y8 24      33 2A8
 GND 25      32 GND
/2Y9 26      31 2A9
2Y10 27      30 2A10
/2O1 28      29 /2O2
     
#
7416833
Dual 8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity register.

      Ŀ
 /1OB 1   56 /1OA
 1CLK 2       55 /1CL
/1ERR 3       54 1PAR
  GND 4       53 GND
  1A1 5       52 1B1
  1A2 6       51 1B2
  VCC 7       50 VCC
  1A3 8       49 1B3
  1A4 9       48 1B4
  1A5 10      47 1B5
  GND 11      46 GND
  1A6 12      45 1B6
  1A7 13      44 1B7
  1A8 14 7416 43 1B8
  2A1 15  833 42 2B1
  2A2 16      41 2B2
  2A3 17      40 2B3
  GND 18      39 GND
  2A4 19      38 2B4
  2A5 20      37 2B5
  2A6 21      36 2B6
  VCC 22      35 VCC
  2A7 23      34 2B7
  2A8 24      33 2B8
  GND 25      32 GND
/2ERR 26      31 2PAR
 2CLK 27      30 /2CL
 /2OB 28      29 /2OA
      
#
7416841
Dual 10-bit 3-state transparent latches.

     Ŀ            Ŀ
/1OE 1   56 1LE        /OE LE D  Q 
 1Q1 2       55 1D1        ͵
 1Q2 3       54 1D2         1  X  X  Z 
 GND 4       53 GND         0  0  X  - 
 1Q3 5       52 1D3         0  1  0  0 
 1Q4 6       51 1D4         0  1  1  1 
 VCC 7       50 VCC        
 1Q5 8       49 1D5
 1Q6 9       48 1D6
 1Q7 10      47 1D7
 GND 11      46 GND
 1Q8 12      45 1D8
 1Q9 13      44 1D9
1Q10 14 7416 43 1D10
 2Q1 15 841  42 2D1
 2Q2 16      41 2D2
 2Q3 17      40 2D3
 GND 18      39 GND
 2Q4 19      38 2D4
 2Q5 20      37 2D5
 2Q6 21      36 2D6
 VCC 22      35 VCC
 2Q7 23      34 2D7
 2Q8 24      33 2D8
 GND 25      32 GND
 2Q9 26      31 2D9
2Q10 27      30 2D10
/2OE 28      29 2LE
     
#
7416853
Dual 8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity latch.

      Ŀ
 /1OB 1   56 /1OA
 /1LE 2       55 /1CL
/1ERR 3       54 1PAR
  GND 4       53 GND
  1A1 5       52 1B1
  1A2 6       51 1B2
  VCC 7       50 VCC
  1A3 8       49 1B3
  1A4 9       48 1B4
  1A5 10      47 1B5
  GND 11      46 GND
  1A6 12      45 1B6
  1A7 13      44 1B7
  1A8 14 7416 43 1B8
  2A1 15  853 42 2B1
  2A2 16      41 2B2
  2A3 17      40 2B3
  GND 18      39 GND
  2A4 19      38 2B4
  2A5 20      37 2B5
  2A6 21      36 2B6
  VCC 22      35 VCC
  2A7 23      34 2B7
  2A8 24      33 2B8
  GND 25      32 GND
/2ERR 26      31 2PAR
 /2LE 27      30 /2CL
 /2OB 28      29 /2OA
      
#
7416861
Dual 10-bit 3-state noninverting bus transceiver.

     Ŀ
/1GB 1   56 /1GA
 1B1 2       55 1A1
 1B2 3       54 1A2
 GND 4       53 GND
 1B3 5       52 1A3
 1B4 6       51 1A4
 VCC 7       50 VCC
 1B5 8       49 1A5
 1B6 9       48 1A6
 1B7 10      47 1A7
 GND 11      46 GND
 1B8 12      45 1A8
 1B9 13      44 1A9
1B10 14 7416 43 1A10
 2B1 15  861 42 2A1
 2B2 16      41 2A2
 2B3 17      40 2A3
 GND 18      39 GND
 2B4 19      38 2A4
 2B5 20      37 2A5
 2B6 21      36 2A6
 VCC 22      35 VCC
 2B7 23      34 2A7
 2B8 24      33 2A8
 GND 25      32 GND
 2B9 26      31 2A9
2B10 27      30 2A10
/2GB 28      29 /2GA
     
#
7416863
Dual 9-bit 3-state noninverting bus transceiver.

     Ŀ
/1GA 1   56 /1GB
 1B1 2       55 1A1
 1B2 3       54 1A2
 GND 4       53 GND
 1B3 5       52 1A3
 1B4 6       51 1A4
 VCC 7       50 VCC
 1B5 8       49 1A5
 1B6 9       48 1A6
 1B7 10      47 1A7
 GND 11      46 GND
 1B8 12      45 1A8
 1B9 13      44 1A9
 GND 14 7416 43 GND
 GND 15  863 42 GND
 2B1 16      41 2A1
 2B2 17      40 2A2
 GND 18      39 GND
 2B3 19      38 2A3
 2B4 20      37 2A4
 2B5 21      36 VCC
 VCC 22      35 2A5
 2B6 23      34 2A6
 2B7 24      33 2A7
 GND 25      32 GND
 2B8 26      31 2A8
 2B9 27      30 2A9
/2GA 28      29 /2GB
     
#
74169
4-bit synchronous binary up/down counter with load and ripple carry output.

     Ŀ
U//D 1   16 VCC
 CLK 2       15 /RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  169  12 Q2
  P3 6       11 Q3
/ENP 7       10 /ENT
 GND 8        9 /LOAD
     
#
7416952
Dual 8-bit 3-state noninverting latched transceiver.

     Ŀ
/1OA 1   56 /1OB
1CKA 2       55 1CKB
/1EA 3       54 /1EB
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  952 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
/2EA 26      31 /2EB
2CKA 27      30 2CKB
/2OA 28      29 /2OB
     
#
7416953
Dual 8-bit 3-state inverting latched transceiver.

     Ŀ
/1OA 1   56 /1OB
1CKA 2       55 1CKB
/1EA 3       54 /1EB
 GND 4       53 GND
 1A1 5       52 1B1
 1A2 6       51 1B2
 VCC 7       50 VCC
 1A3 8       49 1B3
 1A4 9       48 1B4
 1A5 10      47 1B5
 GND 11      46 GND
 1A6 12      45 1B6
 1A7 13      44 1B7
 1A8 14 7416 43 1B8
 2A1 15  952 42 2B1
 2A2 16      41 2B2
 2A3 17      40 2B3
 GND 18      39 GND
 2A4 19      38 2B4
 2A5 20      37 2B5
 2A6 21      36 2B6
 VCC 22      35 VCC
 2A7 23      34 2B7
 2A8 24      33 2B8
 GND 25      32 GND
/2EA 26      31 /2EB
2CKA 27      30 2CKB
/2OA 28      29 /2OB
     
#
7417
Hex open-collector high-voltage buffers.
Maximum output voltage is 15V.

    Ŀ             Ŀ
 1A 1   14 VCC          A  Y           Y = A
 1Y 2       13 6A          ͵
 2A 3       12 6Y           0  0 
 2Y 4  7417 11 5A           1  Z 
 3A 5       10 5Y          
 3Y 6        9 4A
GND 7        8 4Y
    
#
74170
4x4-bit open-collector dual-port register file.

fart 6017
fart 6018

    Ŀ
 D2 1   16 VCC
 D3 2       15 D1
 D4 3       14 WA0
RA1 4   74  13 WA1
RA0 5  170  12 /WR
 Q4 6       11 /RD
 Q3 7       10 Q1
GND 8        9 Q2
    
#
74173
4-bit 3-state D flip-flop with reset, dual clock enables and dual
output enables.

     Ŀ
/OE1 1   16 VCC
/OE2 2       15 RST
  Q0 3       14 D0
  Q1 4   74  13 D1
  Q2 5  173  12 D2
  Q3 6       11 D3
 CLK 7       10 /CLKEN1
 GND 8        9 /CLKEN2
     
#
74174, 40174
6-bit D flip-flop with reset.

     Ŀ            Ŀ
/RST 1   16 VCC        /RSTCLK D  Q 
  Q0 2       15 Q6         ͵
  D0 3       14 D5           0  X  X  0 
  D1 4   74  13 D4           1  /  0  0 
  Q1 5  174  12 Q4           1  /  1  1 
  D2 6       11 D3           1 !/  X  - 
  Q2 7       10 Q3         
 GND 8        9 CLK
     
#
74175
4-bit D flip-flop with complementary outputs and reset.

     Ŀ            Ŀ
/RST 1   16 VCC        /RSTCLK D  Q /Q 
  Q1 2       15 Q4         ͵
 /Q1 3       14 /Q4          0  X  X  0  1 
  D1 4   74  13 D4           1  /  0  0  1 
  D2 5  175  12 D3           1  /  1  1  0 
 /Q2 6       11 /Q3          1 !/  X  -  - 
  Q2 7       10 Q3         
 GND 8        9 CLK
     
#
7418
Dual 4-input NAND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7418 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
74180
8-bit odd/even parity generator/checker with cascade inputs.

      Ŀ
   A0 1   14 VCC
   A1 2       13 A7
 CASE 3   74  12 A6
 CASO 4  180  11 A5
 EVEN 5       10 A4
  ODD 6        9 A3
  GND 7        8 A2
      
#
741804
Hex 2-input NAND gates/line drivers.

    Ŀ             Ŀ           ___
 5B 1   20 5A           A  B /Y       /Y = A+B
/6Y 2       19 /5Y         ͵
 6A 3       18 4B           0  0  1 
 6B 4       17 4A           0  1  1 
VCC 5  741  16 /4Y          1  0  1 
 1A 6  804  15 GND          1  1  0 
 1B 7       14 /3Y         
/1Y 8       13 3B
 2A 9       12 3A
 2B 10      11 /2Y
    
#
741805
Hex 2-input NOR gates/line drivers.

    Ŀ             Ŀ           ___
 5B 1   20 5A           A  B /Y       /Y = A+B
/6Y 2       19 /5Y         ͵
 6A 3       18 4B           0  0  1 
 6B 4       17 4A           0  1  0 
VCC 5  741  16 /4Y          1  0  0 
 1A 6  805  15 GND          1  1  0 
 1B 7       14 /3Y         
/1Y 8       13 3B
 2A 9       12 3A
 2B 10      11 /2Y
    
#
741808
Hex 2-input AND gates/line drivers.

    Ŀ             Ŀ
 5B 1   20 5A           A  B  Y        Y = AB
 6Y 2       19 5Y          ͵
 6A 3       18 4B           0  0  0 
 6B 4       17 4A           0  1  0 
VCC 5  741  16 4Y           1  0  0 
 1A 6  808  15 GND          1  1  1 
 1B 7       14 3Y          
 1Y 8       13 3B
 2A 9       12 3A
 2B 10      11 2Y
    
#
74181, 40181
4-bit 16-function arithmetic logic unit (ALU)

    Ŀ
/B0 1   24 VCC
/A0 2       23 /A1
 S3 3       22 /B1
 S2 4       21 /A2
 S1 5       20 /B2
 S0 6   74  19 /A3
CIN 7  181  18 /B3
  M 8       17 /G
/F0 9       16 COUT
/F1 10      15 /P
/F2 11      14 A=B
GND 12      13 /F3
    
#
74182, 40182
Look-ahead carry generator
Capable of anticipating a carry across four binary adders or group of adders.
Cascadable to perform full look-ahead across n-bit adders.

    Ŀ
/G1 1   16 VCC
/P1 2       15 /P2
/G0 3       14 /G2
/P0 4   74  13 Cn
/G3 5  182  12 Cn+X
/P3 6       11 Cn+Y
 /P 7       10 /G
GND 8        9 Cn+Z
    
#
741821
10-bit 3-state D flip-flop/bus driver.

    Ŀ             Ŀ
 Q5 1   24 Q6          /OECLK D  Q 
 Q4 2       23 Q7          ͵
 Q3 3       22 Q8           1  X  X  Z 
 Q2 4       21 Q9           0  /  0  0 
 Q1 5       20 Q10          0  /  1  1 
VCC 6  741  19 CLK          0 !/  X  - 
/OE 7  821  18 GND         
 D1 8       17 D10
 D2 9       16 D9
 D3 10      15 D8
 D4 11      14 D7
 D5 12      13 D6
    
#
74183
Dual full adder.

    Ŀ           Ŀ
 1A 1   14 VCC        CI A  B    CO
    2       13 2A        ͵
 1B 3  74   12 2B         0  0  0  0  0 
1CI 4  183  11 2CI        0  0  1  1  0 
1CO 5       10 2CO        0  1  0  1  0 
 1 6        9            0  1  1  0  1 
GND 7        8 2         1  0  0  1  0 
                1  0  1  0  1 
                            1  1  0  0  1 
                            1  1  1  1  1 
                           
#
741832
Hex 2-input OR gates/line drivers.

    Ŀ             Ŀ
 5B 1   20 5A           A  B  Y        Y = A+B
 6Y 2       19 5Y          ͵
 6A 3       18 4B           0  0  0 
 6B 4       17 4A           0  1  1 
VCC 5  741  16 4Y           1  0  1 
 1A 6  832  15 GND          1  1  1 
 1B 7       14 3Y          
 1Y 8       13 3B
 2A 9       12 3A
 2B 10      11 2Y
    
#
7419
Hex inverters with schmitt-trigger line-receiver inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ               _
 1A 1   14 VCC          A /Y           /Y = A
/1Y 2       13 6A          ͵
 2A 3       12 /6Y          0  1 
/2Y 4  7414 11 5A           1  0 
 3A 5       10 /5Y         
/3Y 6        9 4A
GND 7        8 /4Y
    
#
74190
4-bit synchronous decade up/down counter with load and both carry out and
ripple clock outputs.

       Ŀ
    P1 1   16 VCC
    Q1 2       15 P0
    Q0 3       14 CLK
/CLKEN 4   74  13 /RCLK
  D//U 5  190  12 /RCO
    Q2 6       11 /LOAD
    Q3 7       10 P2
   GND 8        9 P3
       
#
74191
4-bit synchronous binary up/down counter with load and both carry out and
ripple clock outputs.

       Ŀ
    P1 1   16 VCC
    Q1 2       15 P0
    Q0 3       14 CLK
/CLKEN 4   74  13 /RCLK
  D//U 5  191  12 /RCO
    Q2 6       11 /LOAD
    Q3 7       10 P2
   GND 8        9 P3
       
#
74192, 40192
4-bit synchronous decade up/down counter with asynchronous load and reset,
and separate up and down clocks, carry and borrow outputs.

     Ŀ
  P1 1   16 VCC
  Q1 2       15 P0
  Q0 3       14 RST
DOWN 4   74  13 /BORROW
  UP 5  192  12 /CARRY
  Q2 6       11 /LOAD
  Q3 7       10 P2
 GND 8        9 P3
     
#
74193, 40193
4-bit synchronous binary up/down counter with asynchronous load and reset,
and separate up and down clocks.  Carry and borrow outputs.

     Ŀ
  P1 1   16 VCC
  Q1 2       15 P0
  Q0 3       14 RST
DOWN 4   74  13 /BORROW
  UP 5  193  12 /CARRY
  Q2 6       11 /LOAD
  Q3 7       10 P2
 GND 8        9 P3
     
#
74194
4-bit bidirectional universal shift register with asynchronous reset
and with separate shift left and shift right serial inputs.

     Ŀ
/RST 1   16 VCC
   D 2       15 Q3
  P3 3       14 Q2
  P2 4   74  13 Q1
  P1 5  194  12 Q0
  P0 6       11 CLK
   L 7       10 S1
 GND 8        9 S0
     
#
74195
4-bit shift register with J-/K inputs and asynchronous reset.

     Ŀ
/RST 1   16 VCC
   J 2       15 Q3
  /K 3       14 Q2
  P3 4   74  13 Q1
  P2 5  195  12 Q0
  P1 6       11 /Q0
  P0 7       10 CLK
 GND 8        9 SH//LD
     
#
74196
4-bit asynchronous decade counter with /2 and /5 sections, load and reset.

      Ŀ
/LOAD 1   14 VCC
   Q2 2       13 /RST
   P2 3   74  12 Q3
   P0 4  196  11 P3
   Q0 5       10 P1
/CLK1 6        9 Q1
  GND 7        8 /CLK0
      
#
74197
4-bit asynchronous binary counter with /2 and /8 sections, load and reset.

      Ŀ
/LOAD 1   14 VCC
   Q2 2       13 /RST
   P2 3   74  12 Q3
   P0 4  197  11 P3
   Q0 5       10 P1
/CLK1 6        9 Q1
  GND 7        8 /CLK0
      
#
74198
8-bit bidirectional universal shift register with asynchronous reset and
separate shift left and shift right serial data inputs.

    Ŀ
 S0 1   24 VCC
 SA 2       23 S1
  A 3       22 SH
 QA 4       21 H
  B 5       20 QH
 QB 6   74  19 G
  C 7  198  18 QG
 QC 8       17 F
  D 9       16 QF
 QD 10      15 E
CLK 11      14 QE
GND 12      13 /RST
    
#
7420
Dual 4-input NAND gates.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7420 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
74203
6-line inverting clock driver.

    Ŀ
 1Y 1   20 1A
 2Y 2       19 2A
 3Y 3       18 3A
GND 4       17
GND 5   74  16 VCC
GND 6  203  15 VCC
GND 7       14
 4Y 8       13 4A
 5Y 9       12 5A
 6Y 10      11 6A
    
#
74204
6-line inverting clock driver.

    Ŀ
 1Y 1   20 1A
 2Y 2       19 2A
 3Y 3       18 3A
GND 4       17
GND 5   74  16 VCC
GND 6  204  15 VCC
GND 7       14
 4Y 8       13 4A
 5Y 9       12 5A
 6Y 10      11 6A
    
#
74208
Dual 3-state 1-line to 4-line noninverting clock driver.

    Ŀ
1Y2 1   20 1Y1
1Y3 2       19 1A
1Y4 3       18 /1OE1
GND 4       17 /1OE2
GND 5   74  16 VCC
GND 6  208  15 VCC
GND 7       14 2A
2Y1 8       13 /2OE1
2Y2 9       12 /2OE2
2Y3 10      11 2Y4
    
#
74209
Dual 3-state 1-line to 4-line noninverting clock driver.

    Ŀ
1Y2 1   20 1Y1
1Y3 2       19 1A
1Y4 3       18 /1OE1
GND 4       17 /1OE2
GND 5   74  16 VCC
GND 6  209  15 VCC
GND 7       14 2A
2Y1 8       13 /2OE1
2Y2 9       12 /2OE2
2Y3 10      11 2Y4
    
#
7421
Dual 4-input AND gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  C  D  Y     Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  0 
 1C 4  7421 11              1  0  X  X  0 
 1D 5       10 2B           1  1  0  X  0 
 1Y 6        9 2A           1  1  1  0  0 
GND 7        8 2Y           1  1  1  1  1 
                 
#
7422
Dual 4-input open-collector NAND gates.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  Z 
 1C 4  7422 11              1  0  X  X  Z 
 1D 5       10 2B           1  1  0  X  Z 
/1Y 6        9 2A           1  1  1  0  Z 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
74221
Dual monostable multivibrators with Schmitt-trigger inputs.

       Ŀ
  /1TR 1   16 VCC
   1TR 2       15 1RCext
 /1RST 3       14 1Cext
   /1Q 4   74  13 1Q
    2Q 5  221  12 /2Q
 2Cext 6       11 /2RST
2RCext 7       10 2TR
   GND 8        9 /2TR
       
#
742240
Dual 4-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
/2Y4 3       18 /1Y1
 1A2 4       17 2A4
/2Y3 5  742  16 /1Y2
 1A3 6  240  15 2A3
/2Y2 7       14 /1Y3
 1A4 8       13 2A2
/2Y1 9       12 /1Y4
 GND 10      11 2A1
     
#
742241
Dual 4-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.
One active low, one active high output enable.

     Ŀ
/1OE 1   20 VCC
 1A4 2       19 2OE
 2Y1 3       18 1Y1
 1A3 4       17 2A4
 2Y2 5  742  16 1Y2
 1A2 6  241  15 2A3
 2Y3 7       14 1Y3
 1A1 8       13 2A2
 2Y4 9       12 1Y4
 GND 10      11 2A1
     
#
742244
Dual 4-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
 2Y4 3       18 1Y1
 1A2 4       17 2A4
 2Y3 5  742  16 1Y2
 1A3 6  244  15 2A3
 2Y2 7       14 1Y3
 1A4 8       13 2A2
 2Y1 9       12 1Y4
 GND 10      11 2A1
     
#
742245
8-bit 3-state noninverting bus transceiver with integrated 25 series
output resistors.
Enable and direction pins control output enables.

    Ŀ             Ŀ
DIR 1   20 VCC         /ENDIR A  B 
 A0 2       19 /EN         ͵
 A1 3       18 B0           1  X  Z  Z 
 A2 4       17 B1           0  0  B  Z 
 A3 5  742  16 B2           0  1  Z  A 
 A4 6  245  15 B3          
 A5 7       14 B4
 A6 8       13 B5
 A7 9       12 B6
GND 10      11 B7
    
#
74237
1-of-8 noninverting decoder/demultiplexer with address latches.

     Ŀ
  S0 1   16 VCC
  S1 2       15 Y0
  S2 3       14 Y1
 /LE 4   74  13 Y2
/EN2 5  237  12 Y3
 EN1 6       11 Y4
  Y7 7       10 Y5
 GND 8        9 Y6
     
#
74238
1-of-8 noninverting decoder/demultiplexer.

     Ŀ            Ŀ
  S0 1   16 VCC        EN1/EN2/EN3 S2 S1 S0/Y0/Y1.../Y7
  S1 2       15 Y0         ͵
  S2 3       14 Y1          0  X    X  X  X  X  0  0  0  0 
/EN3 4   74  13 Y2          1  1    X  X  X  X  0  0  0  0 
/EN2 5  238  12 Y3          1  0    1  X  X  X  0  0  0  0 
 EN1 6       11 Y4          1  0    0  0  0  0  1  0  0  0 
  Y7 7       10 Y5          1  0    0  0  0  1  0  1  0  0 
 GND 8        9 Y6          1  0    0  .  .  .  0  0  .  0 
                  1  0    0  1  1  1  0  0  0  1 
                             
#
74239
Dual 1-of-4 noninverting decoder/demultiplexer.

     Ŀ            Ŀ
/1EN 1   16 VCC        /EN S1 S0 Y0 Y1 Y2 Y3
 1S0 2       15 /2EN       ͵
 1S1 3       14 2S0         1  X  X  0  0  0  0 
 1Y0 4   74  13 2S1         0  0  0  1  0  0  0 
 1Y1 5  239  12 2Y0         0  0  1  0  1  0  0 
 1Y2 6       11 2Y1         0  1  0  0  0  1  0 
 1Y3 7       10 2Y2         0  1  1  0  0  0  1 
 GND 8        9 2Y3        
     
#
7424
Quad 2-input NAND gates with schmitt-trigger line-receiver inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4  7424 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
74240
Dual 4-bit 3-state inverting buffer/line driver.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
/2Y4 3       18 /1Y1
 1A2 4       17 2A4
/2Y3 5  74   16 /1Y2
 1A3 6  240  15 2A3
/2Y2 7       14 /1Y3
 1A4 8       13 2A2
/2Y1 9       12 /1Y4
 GND 10      11 2A1
     
#
74241
Dual 4-bit 3-state noninverting buffer/line driver.
One active low, one active high output enable.

     Ŀ
/1OE 1   20 VCC
 1A4 2       19 2OE
 2Y1 3       18 1Y1
 1A3 4       17 2A4
 2Y2 5  74   16 1Y2
 1A2 6  241  15 2A3
 2Y3 7       14 1Y3
 1A1 8       13 2A2
 2Y4 9       12 1Y4
 GND 10      11 2A1
     
#
742410
11-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
  A1 1   28 A6
  A2 2       27 A7
  A3 3       26 A8
  A4 4       25 A9
  A5 5       24 A10
/OE1 6       23 A11
 VCC 7  742  22 GND
 GND 8  410  21 GND
/OE2 9       20 Y11
  Y5 10      19 Y10
  Y4 11      18 Y9
  Y3 12      17 Y8
  Y2 13      16 Y7
  Y1 14      15 Y6
     
#
742411
11-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
  A1 1   28 A6
  A2 2       27 A7
  A3 3       26 A8
  A4 4       25 A9
  A5 5       24 A10
/OE1 6       23 A11
 VCC 7  742  22 GND
 GND 8  411  21 GND
/OE2 9       20/Y11
 /Y5 10      19/Y10
 /Y4 11      18/Y9
 /Y3 12      17/Y8
 /Y2 13      16/Y7
 /Y1 14      15/Y6
     
#
74242
4-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

     Ŀ
/GAB 1   14 VCC
     2       13 GBA
  A1 3  74   12
  A2 4  242  11 B1
  A3 5       10 B2
  A4 6        9 B3
 GND 7        8 B4
     
#
74243
4-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

     Ŀ
/GAB 1   14 VCC
     2       13 GBA
  A1 3  74   12
  A2 4  243  11 B1
  A3 5       10 B2
  A4 6        9 B3
 GND 7        8 B4
     
#
74244
Dual 4-bit 3-state noninverting buffer/line driver.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
 2Y4 3       18 1Y1
 1A2 4       17 2A4
 2Y3 5  74   16 1Y2
 1A3 6  244  15 2A3
 2Y2 7       14 1Y3
 1A4 8       13 2A2
 2Y1 9       12 1Y4
 GND 10      11 2A1
     
#
74245
8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ             Ŀ
DIR 1   20 VCC         /ENDIR A  B 
 A1 2       19 /EN         ͵
 A2 3       18 B1           1  X  Z  Z 
 A3 4       17 B2           0  0  B  Z 
 A4 5  74   16 B3           0  1  Z  A 
 A5 6  245  15 B4          
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74247
Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple
blank input and output.

     Ŀ
  A1 1   16 VCC
  A2 2       15 /YF
 /LT 3       14 /YG
/RBO 4  74   13 /YA
/RBI 5  247  12 /YB
  A3 6       11 /YC
  A0 7       10 /YD
 GND 8        9 /YE
     
#
74248
BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and
output.

     Ŀ
  A1 1   16 VCC
  A2 2       15 YF
 /LT 3       14 YG
/RBO 4  74   13 YA
/RBI 5  248  12 YB
  A3 6       11 YC
  A0 7       10 YD
 GND 8        9 YE
     
#
7425
Dual 4-input NOR gates with enable input.

    Ŀ                 __________
 1A 1   14 VCC         Y = G(A+B+C+D)
 1B 2       13 2D
 1G 3       12 2C
 1C 4  7425 11 2G
 1D 5       10 2B
/1Y 6        9 2A
GND 7        8 /2Y
    
#
74251
8-to-1 line 3-state data selector/multiplexer with complementary outputs.

    Ŀ
 A3 1   16 VCC
 A2 2       15 A4
 A1 3       14 A5
 A0 4   74  13 A6
  Y 5  251  12 A7
 /Y 6       11 S0
/EN 7       10 S1
GND 8        9 S2
    
#
7425240
Dual 4-bit 3-state inverting buffer/bus driver with integrated 25 series
output resistors.  Increased drive to drive 25 bus.

     Ŀ
/1Y1 1   24 /1OE
 GND 2       23 1A1
/1Y2 3       22 1A2
/1Y3 4       21 VCC
 GND 5       20 1A3
/1Y4 6 7425  19 1A4
/2Y1 7  240  18 2A1
 GND 8       17 2A2
/2Y2 9       16 VCC
/2Y3 10      15 2A3
 GND 11      14 2A4
/2Y4 12      13 /2OE
     
#
7425244
Dual 4-bit 3-state noninverting buffer/bus driver with integrated 25 series
output resistors.  Increased drive to drive 25 bus.

    Ŀ
1Y1 1   24 /1OE
GND 2       23 1A1
1Y2 3       22 1A2
1Y3 4       21 VCC
GND 5       20 1A3
1Y4 6 7425  19 1A4
2Y1 7  240  18 2A1
GND 8       17 2A2
2Y2 9       16 VCC
2Y3 10      15 2A3
GND 11      14 2A4
2Y4 12      13 /2OE
    
#
7425245
8-bit 3-state noninverting bus transceiver with integrated 25 series
output resistors.  Increased drive to drive 25 bus.
Enable and direction pins control output enables.

    Ŀ             Ŀ
 A1 1   24 DIR         /ENDIR A  B 
GND 2       23 B1          ͵
 A2 3       22 B2           1  X  Z  Z 
 A3 4       21 VCC          0  0  B  Z 
GND 5       20 B3           0  1  Z  A 
 A4 6 7425  19 B4          
 A5 7  245  18 B5
GND 8       17 B6
 A6 9       16 VCC
 A7 10      15 B7
GND 11      14 B8
 A8 12      13 /EN
    
#
74253
8-to-2 line 3-state noninverting data selector/multiplexer.

     Ŀ
/1EN 1   16 VCC
  S1 2       15 /2EN
 1A3 3       14 S0
 1A2 4   74  13 2A3
 1A1 5  253  12 2A2
 1A0 6       11 2A1
  1Y 7       10 2A0
 GND 8        9 2Y
     
#
74256
2-of-8 addressable latch with reset and enable.

     Ŀ            Ŀ
  S0 1   16 VCC        /EN/RST Function           
  S1 2       15 /RST       ͵
  1D 3       14 /EN         0   0  2-of-8 demultiplex 
 1Q0 4  74   13 2D          0   1  addressable latch  
 1Q1 5  256  12 2Q3         1   0  reset              
 1Q2 6       11 2Q2         1   1  hold               
 1Q3 7       10 2Q1        
 GND 8        9 2Q0
     
#
7425642
8-bit open-collector inverting bus transceiver.
Enable and direction pins control output enables.
Increased drive to drive 25 bus.

    Ŀ
 A1 1   24 DIR
GND 2       23 B1
 A2 3       22 B2
 A3 4       21 VCC
GND 5       20 B3
 A4 6 7425  19 B4
 A5 7  642  18 B5
GND 8       17 B6
 A6 9       16 VCC
 A7 10      15 B7
GND 11      14 B8
 A8 12      13 /OE
    
#
74257, 40257
8-to-4 line 3-state noninverting data selector/multiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
 1Y 4   74  13 4A1
2A0 5  257  12 4Y
2A1 6       11 3A0
 2Y 7       10 3A1
GND 8        9 3Y
    
#
742574
8-bit 3-state D flip-flop with integrated 25 series output resistors.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D  Q 
 D1 2       19 Q1          ͵
 D2 3       18 Q2           1  X  X  Z 
 D3 4       17 Q3           0  /  0  0 
 D4 5  742  16 Q4           0  /  1  1 
 D5 6  574  15 Q5           0 !/  X  - 
 D6 7       14 Q6          
 D7 8       13 Q7
 D8 9       12 Q8
GND 10      11 CLK
    
#
74258
8-to-4 line 3-state inverting data selector/multiplexer.

    Ŀ
  S 1   16 VCC
1A0 2       15 /EN
1A1 3       14 4A0
/1Y 4   74  13 4A1
2A0 5  258  12 /4Y
2A1 6       11 3A0
/2Y 7       10 3A1
GND 8        9 /3Y
    
#
74259
1-of-8 addressable latch with reset.

    Ŀ             Ŀ
 S0 1   16 VCC         /EN/RST Function           
 S1 2       15 /RST        ͵
 S2 3       14 /EN          0   0  1-of-8 demultiplex 
 Q0 4   74  13 D            0   1  addressable latch  
 Q1 5  259  12 Q7           1   0  reset              
 Q2 6       11 Q6           1   1  hold               
 Q3 7       10 Q5          
GND 8        9 Q4
    
#
7426
Quad 2-input open-collector high-voltage NAND gates.
Maximum output voltage is 15V.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  Z 
 2A 4  7426 11 /4Y          0  1  Z 
 2B 5       10 3B           1  0  Z 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
74260
Dual 5-input NOR gates.

    Ŀ                 ___________
 1A 1   14 VCC         Y = (A+B+C+D+E)
 1B 2       13 2D
 1E 3   74  12 2C
 1C 4  260  11 2E
 1D 5       10 2B
/1Y 6        9 2A
GND 7        8 /2Y
    
#
74265
Dual buffer/inverter plus dual AND/NAND gates.

    Ŀ
 1A 1   16 VCC         1Y=1A
 1Y 2       15 4A
/1Y 3       14 4Y          2Y=2A2B
 2A 4   74  13 /4Y
 2B 5  265  12 3B          3Y=3A3B
 2Y 6       11 3A
/2Y 7       10 3Y          4Y=4A
GND 8        9 /3Y
    
#
74266
Quad 2-input open-collector XNOR gates.

    Ŀ             Ŀ           _ 
 1A 1   14 VCC          A  B /Y      /Y = A$B
 1B 2       13 4B          ͵
/1Y 3  74   12 4A           0  0  Z 
 2A 4  266  11 /4Y          0  1  0 
 2B 5       10 3B           1  0  0 
/2Y 6        9 3A           1  1  Z 
GND 7        8 /3Y         
    
#
7427
Triple 3-input NOR gates.

    Ŀ             Ŀ       _____
 1A 1   14 VCC          A  B  C /Y   /Y = A+B+C
 1B 2       13 1C          ͵
 2A 3       12 /1Y          0  0  0  1 
 2B 4  7427 11 3C           0  0  1  0 
 2C 5       10 3B           0  1  X  0 
/2Y 6        9 3A           1  X  X  0 
GND 7        8 /3Y         
    
#
74273

     Ŀ            Ŀ
/RST 1   20 VCC        /RSTCLK D  Q 
  1Q 2       19 8Q         ͵
  1D 3       18 8D           0  X  X  0 
  2D 4       17 7D           1  /  0  0 
  2Q 5   74  16 7Q           1  /  1  1 
  3Q 6  273  15 6Q         
  3D 7       14 6D
  4D 8       13 5D
  4Q 9       12 5Q
 GND 10      11 CLK
     
#
74276
Quad J-K and J-/K flip-flops with common set and reset.

      Ŀ
 /RST 1   20 VCC
   1J 2       19 4J
/1CLK 3       18 /4CLK
  /1K 4       17 4K
   1Q 5   74  16 4Q
   2Q 6  276  15 3Q
  /2K 7       14 /3K
/2CLK 8       13 /3CLK
   2J 9       12 3J
  GND 10      11 /SET
      
#
74279
Quad /S-/R latches.

     Ŀ
 /1R 1   16 VCC
/1S1 2       15 /4S
/1S2 3       14 /4R
  1Q 4   74  13 4Q
 /2R 5  279  12 /3S2
 /2S 6       11 /3S1
  2Q 7       10 /3R
 GND 8        9 3Q
     
#
7428
Quad 2-input NOR gates with buffered outputs.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  1 
/2Y 4  7428 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
74280
9-bit odd/even parity generator/checker.

      Ŀ
   A0 1   14 VCC
   A1 2       13 A8
      3   74  12 A7
   A2 4  280  11 A6
 EVEN 5       10 A5
  ODD 6        9 A4
  GND 7        8 A3
      
#
742827
10-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/OE1 1   24 VCC
  A1 2       23 Y1
  A2 3       22 Y2
  A3 4       21 Y3
  A4 5       20 Y4
  A5 6  742  19 Y5
  A6 7  827  18 Y6
  A7 8       17 Y7
  A8 9       16 Y8
  A9 10      15 Y9
 A10 11      14 Y10
 GND 12      13 /OE2
     
#
742828
10-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
/OE1 1   24 VCC
  A1 2       23 /Y1
  A2 3       22 /Y2
  A3 4       21 /Y3
  A4 5       20 /Y4
  A5 6  742  19 /Y5
  A6 7  828  18 /Y6
  A7 8       17 /Y7
  A8 9       16 /Y8
  A9 10      15 /Y9
 A10 11      14 /Y10
 GND 12      13 /OE2
     
#
74283
4-bit binary full adder with fast carry.

    Ŀ
 2 1   16 VCC         =A+B+CIN
 B2 2       15 B3
 A2 3       14 A3
 1 4   74  13 3
 A1 5  283  12 A4
 B1 6       11 B4
CIN 7       10 4
GND 8        9 COUT
    
#
74285
4-bit binary multiplier with open-collector outputs.

    Ŀ
 2C 1   16 VCC
 2B 2       15 2D
 2A 3       14 /GA
 1D 4   74  13 /GB
 1A 5  285  12 Y0
 1B 6       11 Y1
 1C 7       10 Y2
GND 8        9 Y3
    
#
74286
9-bit odd/even parity generator/checker with bus driver parity I/O port.

      Ŀ
   A0 1   14 VCC
   A1 2       13 A8
/XMIT 3   74  12 A7
   A2 4  286  11 A6
ERROR 5       10 A5
 PI/O 6        9 A4
  GND 7        8 A3
      
#
74290
4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.
(my databook mentions 'HIGH CUNT RATES' here)

     Ŀ
SET1 1   14 VCC
     2       13 RST2
SET2 3   74  12 RST1
  Q2 4  290  11 /CLK1
  Q1 5       10 /CLK0
     6        9 Q0
 GND 7        8 Q3
     
#
74292
15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.

     Ŀ
   B 1   16 VCC
   E 2       15 C
 TP1 3       14 D
CLK1 4  74   13 TP3
CLK2 5  292  12
 TP2 6       11 /RST
   Q 7       10 A
 GND 8        9
     
#
74293
4-bit asynchronous binary counter with /2 and /8 sections and reset.

     Ŀ
     1   14 VCC
     2       13 RST2
     3       12 RST1
  Q2 4  74   11 /CLK1
  Q1 5  293  10 /CLK0
     6        9 Q0
 GND 7        8 Q3
     
#
74294
15-bit programmable frequency divider/digital timer.
Digitally programmable from 2^2 to 2^15.

     Ŀ
   B 1   16 VCC
   A 2       15 C
  TP 3       14 D
CLK1 4  74   13
CLK2 5  294  12
     6       11 /RST
   Q 7       10
 GND 8        9
     
#
74295
4-bit 3-state negative-edge-triggered shift register.

      Ŀ
   SA 1   14 VCC
    A 2       13 QA
    B 3       12 QB
    C 4  74   11 QC
    D 5  295  10 QD
L//SH 6        9 /CLK
  GND 7        8 EN
      
#
742952
8-bit 3-state noninverting latched transceiver.

      Ŀ
   B8 1   24 VCC
   B7 2       23 A8
   B6 3       22 A7
   B5 4       21 A6
   B4 5       20 A5
   B3 6  742  19 A4
   B2 7  952  18 A3
   B1 8       17 A2
/OEAB 9       16 A1
CLKAB 10      15 /OEBA
/CEAB 11      14 CLKBA
  GND 12      13 /CEBA
      
#
742953
8-bit 3-state inverting latched transceiver.

      Ŀ
   B8 1   24 VCC
   B7 2       23 A8
   B6 3       22 A7
   B5 4       21 A6
   B4 5       20 A5
   B3 6  742  19 A4
   B2 7  953  18 A3
   B1 8       17 A2
/OEAB 9       16 A1
CLKAB 10      15 /OEBA
/CEAB 11      14 CLKBA
  GND 12      13 /CEBA
      
#
74298
8-to-4 line noninverting data selector/multiplexer with output registers.

    Ŀ
2A1 1   16 VCC
2A0 2       15 1Q
1A0 3       14 2Q
1A1 4   74  13 3Q
3A1 5  298  12 4Q
4A1 6       11 CLK
4A0 7       10 S
GND 8        9 3A0
    
#
7429818
8-bit 3-state noninverting diagnostics/pipeline register.

      Ŀ
 /OEY 1   24 VCC
SRCLK 2       23 MODE
  DQ0 3       22 Y0
  DQ1 4       21 Y1
  DQ2 5       20 Y2
  DQ3 6 7429  19 Y3
  DQ4 7  818  18 Y4
  DQ5 8       17 Y5
  DQ6 9       16 Y6
  DQ7 10      15 Y7
  SDI 11      14 SDO
  GND 12      13 ORCLK
      
#
7429821
10-bit 3-state D flip-flop/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OECLK D  Q 
 D1 2       23 Q1          ͵
 D2 3       22 Q2           1  X  X  Z 
 D3 4       21 Q3           0  /  0  0 
 D4 5       20 Q4           0  /  1  1 
 D5 6 7429  19 Q5           0 !/  X  - 
 D6 7  821  18 Q6          
 D7 8       17 Q7
 D8 9       16 Q8
 D9 10      15 Q9
D10 11      14 Q10
GND 12      13 CLK
    
#
7429822
10-bit 3-state inverting D flip-flop/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OECLK D /Q 
 D1 2       23 /Q1         ͵
 D2 3       22 /Q2          1  X  X  Z 
 D3 4       21 /Q3          0  /  0  1 
 D4 5       20 /Q4          0  /  1  0 
 D5 6 7429  19 /Q5          0 !/  X  - 
 D6 7  822  18 /Q6         
 D7 8       17 /Q7
 D8 9       16 /Q8
 D9 10      15 /Q9
D10 11      14 /Q10
GND 12      13 CLK
    
#
7429823
9-bit 3-state D flip-flop/bus driver with clock enable and reset.

     Ŀ
 /OE 1   24 VCC
  D1 2       23 Q1
  D2 3       22 Q2
  D3 4       21 Q3
  D4 5       20 Q4
  D5 6 7429  19 Q5
  D6 7  823  18 Q6
  D7 8       17 Q7
  D8 9       16 Q8
  D9 10      15 Q9
/RST 11      14 /CLKEN
 GND 12      13 CLK
     
#
7429825
8-bit 3-state D flip-flop/bus driver with three output enables, clock enable
and reset.

     Ŀ
/OE1 1   24 VCC
/OE2 2       23 /OE3
  D1 3       22 Q1
  D2 4       21 Q2
  D3 5       20 Q3
  D4 6 7429  19 Q4
  D5 7  825  18 Q5
  D6 8       17 Q6
  D7 9       16 Q7
  D8 10      15 Q8
/RST 11      14 /CLKEN
 GND 12      13 CLK
     
#
7429826
8-bit 3-state inverting D flip-flop/bus driver with three output enables,
clock enable and reset.

     Ŀ
/OE1 1   24 VCC
/OE2 2       23 /OE3
  D0 3       22 /Q0
  D1 4       21 /Q1
  D2 5       20 /Q2
  D3 6 7429  19 /Q3
  D4 7  826  18 /Q4
  D5 8       17 /Q5
  D6 9       16 /Q6
  D7 10      15 /Q7
/RST 11      14 /CLKEN
 GND 12      13 CLK
     
#
7429827
10-bit 3-state noninverting buffer/line driver.

     Ŀ
/OE1 1   24 VCC
  A0 2       23 Y0
  A1 3       22 Y1
  A2 4       21 Y2
  A3 5       20 Y3
  A4 6 7429  19 Y4
  A5 7  827  18 Y5
  A6 8       17 Y6
  A7 9       16 Y7
  A8 10      15 Y8
  A9 11      14 Y9
 GND 12      13 /OE2
     
#
7429828
10-bit 3-state inverting buffer/line driver.

     Ŀ
/OE1 1   24 VCC
  A0 2       23 /Y0
  A1 3       22 /Y1
  A2 4       21 /Y2
  A3 5       20 /Y3
  A4 6 7429  19 /Y4
  A5 7  828  18 /Y5
  A6 8       17 /Y6
  A7 9       16 /Y7
  A8 10      15 /Y8
  A9 11      14 /Y9
 GND 12      13 /OE2
     
#
7429833
8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity register.

       Ŀ
  /OEA 1   24 VCC
    A0 2       23 B0
    A1 3       22 B1
    A2 4       21 B2
    A3 5       20 B3
    A4 6 7429  19 B4
    A5 7  833  18 B5
    A6 8       17 B6
    A7 9       16 B7
/ERROR 10      15 PAR
  /CLR 11      14 /OEB
   GND 12      13 CLK
       
#
7429834
8-bit 3-state inverting bus transceiver with parity generator/checker
and parity register.

       Ŀ
  /OEA 1   24 VCC
    A0 2       23 B0
    A1 3       22 B1
    A2 4       21 B2
    A3 5       20 B3
    A4 6 7429  19 B4
    A5 7  834  18 B5
    A6 8       17 B6
    A7 9       16 B7
/ERROR 10      15 PAR
  /CLR 11      14 /OEB
   GND 12      13 CLK
       
#
7429841
10-bit 3-state transparent latch/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OE LE D  Q 
 D0 2       23 Q0          ͵
 D1 3       22 Q1           1  X  X  Z 
 D2 4       21 Q2           0  0  X  - 
 D3 5       20 Q3           0  1  0  0 
 D4 6 7429  19 Q4           0  1  1  1 
 D5 7  841  18 Q5          
 D6 8       17 Q6
 D7 9       16 Q7
 D8 10      15 Q8
 D9 11      14 Q9
GND 12      13 LE
    
#
7429842
10-bit 3-state inverting transparent latch/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OE LE D /Q 
 D0 2       23 /Q0         ͵
 D1 3       22 /Q1          1  X  X  Z 
 D2 4       21 /Q2          0  0  X  - 
 D3 5       20 /Q3          0  1  0  1 
 D4 6 7429  19 /Q4          0  1  1  0 
 D5 7  842  18 /Q5         
 D6 8       17 /Q6
 D7 9       16 /Q7
 D8 10      15 /Q8
 D9 11      14 /Q9
GND 12      13 LE
    
#
7429843
9-bit 3-state transparent latch/bus driver with set and reset.

     Ŀ            Ŀ
 /OE 1   24 VCC        /RST/SET/OE LE D  Q 
  D0 2       23 Q0         ͵
  D1 3       22 Q1           0   1  0  X  X  0 
  D2 4       21 Q2           1   0  0  X  X  0 
  D3 5       20 Q3           X   X  1  X  X  Z 
  D4 6 7429  19 Q4           1   1  0  0  X  - 
  D5 7  843  18 Q5           1   1  0  1  0  0 
  D6 8       17 Q6           1   1  0  1  1  1 
  D7 9       16 Q7         
  D8 10      15 Q8
/RST 11      14 /SET
 GND 12      13 LE
     
#
7429844
9-bit 3-state inverting transparent latch/bus driver with set and reset.

     Ŀ
 /OE 1   24 VCC
  D0 2       23 /Q0
  D1 3       22 /Q1
  D2 4       21 /Q2
  D3 5       20 /Q3
  D4 6 7429  19 /Q4
  D5 7  844  18 /Q5
  D6 8       17 /Q6
  D7 9       16 /Q7
  D8 10      15 /Q8
/RST 11      14 /SET
 GND 12      13 LE
     
#
7429846
8-bit 3-state inverting transparent latch/bus driver with three output
enables, set and reset.

     Ŀ
/OE1 1   24 VCC
/OE2 2       23 /OE3
  D1 3       22 /Q1
  D2 4       21 /Q2
  D3 5       20 /Q3
  D4 6 7429  19 /Q4
  D5 7  846  18 /Q5
  D6 8       17 /Q6
  D7 9       16 /Q7
  D8 10      15 /Q8
/RST 11      14 /SET
 GND 12      13 LE
     
#
7429853
8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity latch.

       Ŀ
  /OEA 1   24 VCC
    A0 2       23 B0
    A1 3       22 B1
    A2 4       21 B2
    A3 5       20 B3
    A4 6 7429  19 B4
    A5 7  853  18 B5
    A6 8       17 B6
    A7 9       16 B7
/ERROR 10      15 PAR
  /CLR 11      14 /OEB
   GND 12      13 /LE
       
#
7429854
8-bit 3-state inverting bus transceiver with parity generator/checker
and parity latch.

       Ŀ
  /OEA 1   24 VCC
    A0 2       23 B0
    A1 3       22 B1
    A2 4       21 B2
    A3 5       20 B3
    A4 6 7429  19 B4
    A5 7  853  18 B5
    A6 8       17 B6
    A7 9       16 B7
/ERROR 10      15 PAR
  /CLR 11      14 /OEB
   GND 12      13 /LE
       
#
7429861
10-bit 3-state noninverting bus transceiver.

     Ŀ
/GBA 1   24 VCC
  A1 2       23 B1
  A2 3       22 B2
  A3 4       21 B3
  A4 5       20 B4
  A5 6 7429  19 B5
  A6 7  861  18 B6
  A7 8       17 B7
  A8 9       16 B8
  A9 10      15 B9
 A10 11      14 B10
 GND 12      13 /GAB
     
#
7429862
10-bit 3-state inverting bus transceiver.

     Ŀ
/GBA 1   24 VCC
  A1 2       23 B1
  A2 3       22 B2
  A3 4       21 B3
  A4 5       20 B4
  A5 6 7429  19 B5
  A6 7  862  18 B6
  A7 8       17 B7
  A8 9       16 B8
  A9 10      15 B9
 A10 11      14 B10
 GND 12      13 /GAB
     
#
7429863
9-bit 3-state noninverting bus transceiver.

      Ŀ
/GBA1 1   24 VCC
   A1 2       23 B1
   A2 3       22 B2
   A3 4       21 B3
   A4 5       20 B4
   A5 6 7429  19 B5
   A6 7  863  18 B6
   A7 8       17 B7
   A8 9       16 B8
   A9 10      15 B9
/GBA2 11      14 /GAB2
  GND 12      13 /GAB1
      
#
7429864
9-bit 3-state inverting bus transceiver.

      Ŀ
/GBA1 1   24 VCC
   A1 2       23 B1
   A2 3       22 B2
   A3 4       21 B3
   A4 5       20 B4
   A5 6 7429  19 B5
   A6 7  864  18 B6
   A7 8       17 B7
   A8 9       16 B8
   A9 10      15 B9
/GBA2 11      14 /GAB2
  GND 12      13 /GAB1
      
#
74299
8-bit 3-state bidirectional universal shift/storage register with asynchronous
reset and with separate shift left and shift right serial inputs.  Multiplexed
parallel I/O.

     Ŀ
  S0 1   20 VCC
/OE1 2       19 S1
/OE2 3       18 SH
  PG 4       17 QH
  PE 5   74  16 PH
  PC 6  299  15 PF
  PA 7       14 PD
  QA 8       13 PB
/RST 9       12 CLK
 GND 10      11 SA
     
#
7430
8-input NAND gate.

    Ŀ                 ________
  A 1   14 VCC        /Y = ABCDEFGH
  B 2       13
  C 3       12 H
  D 4  7430 11 G
  E 5       10
  F 6        9
GND 7        8 /Y
    
#
74303
8-line inverting/noninverting divide by 2 clock driver.
Six outputs in phase with CLK, two out of phase.

    Ŀ
 Q3 1   16 Q2
 Q4 2       15 Q1
GND 3       14 /RST
GND 4   74  13 VCC
GND 5  303  12 VCC
 Q5 6       11 CLK
 Q6 7       10 /PRE
/Q7 8        9 /Q8
    
#
74304
8-line noninverting divide by 2 clock driver.

    Ŀ
 Q3 1   16 Q2
 Q4 2       15 Q1
GND 3       14 /RST
GND 4   74  13 VCC
GND 5  304  12 VCC
 Q5 6       11 CLK
 Q6 7       10 /PRE
 Q7 8        9 Q8
    
#
74305
8-line inverting/noninverting divide by 2 clock driver.
Four outputs in phase with CLK, four out of phase.

    Ŀ
 Q3 1   16 Q2
 Q4 2       15 Q1
GND 3       14 /RST
GND 4   74  13 VCC
GND 5  305  12 VCC
/Q5 6       11 CLK
/Q6 7       10 /PRE
/Q7 8        9 /Q8
    
#
74306
2-bit 3-state noninverting buffer/line driver.

     Ŀ            Ŀ
/1OE 1    8 1Y          A /OE Y 
  1A 2   74   7 VCC        ͵
 GND 3  306   6 1A          0  0  0 
/2OE 4        5 2Y          1  0  1 
                  X  1  Z 
                             
#
7431
Hex delay elements.
Typical delays are 27.5ns (1,6), 46.5ns (2,5), 6ns (3,4).
Improved output currents IoH=-1.2mA, IoL=24mA for gates 3 and 4.

    Ŀ                 _            _____
 1A 1   16 VCC        /1Y=1A        /4Y=4A4B
/1Y 2       15 6A
 2A 3       14 /6Y         2Y=2A         5Y=5A
 2Y 4       13 5A             _____          _
 3A 5  7431 12 5Y         /3Y=3A3B     /6Y=6A
 3B 6       11 4B
/3Y 7       10 4A
GND 8        9 /4Y
    
#
7432
Quad 2-input OR gates.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = A+B
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7432 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    
#
74322
8-bit 3-state shift register with with sign extension and selectable serial
inputs.  Multiplexed parallel I/O.

     Ŀ
 /OE 1   20 VCC
S//P 2       19 DS
  D0 3       18 /SE
  PA 4       17 D1
  PC 5   74  16 PB
  PE 6  322  15 PD
  PG 7       14 PF
 /OE 8       13 PH
/RST 9       12 QH
 GND 10      11 CLK
     
#
74323
8-bit 3-state bidirectional universal shift/storage register with reset and
with separate shift left and shift right serial inputs.  Multiplexed
parallel I/O.

     Ŀ
  S0 1   20 VCC
/OE1 2       19 S1
/OE2 3       18 SH
  PG 4       17 QH
  PE 5   74  16 PH
  PC 6  323  15 PF
  PA 7       14 PD
  QA 8       13 PB
/RST 9       12 CLK
 GND 10      11 SA
     
#
74328
6-line selectable phase clock driver.

    Ŀ
GND 1   16 1Y1
1Y2 2       15 SEL1
2Y1 3       14 VCC
GND 4   74  13 SEL2
2Y2 5  328  12 A
3Y1 6       11 VCC
GND 7       10 SEL3
4Y1 8        9 SEL4
    
#
74329
6-line selectable phase clock driver.

    Ŀ
GND 1   16 1Y1
1Y2 2       15 SEL1
2Y1 3       14 VCC
GND 4   74  13 SEL2
2Y2 5  329  12 A
3Y1 6       11 VCC
GND 7       10 SEL3
4Y1 8        9 SEL4
    
#
7433
Quad 2-input open-collector NOR gates.

    Ŀ             Ŀ           ___
/1Y 1   14 VCC          A  B /Y       /Y = A+B
 1A 2       13 /4Y         ͵
 1B 3       12 4B           0  0  Z 
/2Y 4  7433 11 4A           0  1  0 
 2A 5       10 /3Y          1  0  0 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
74330
Dual 1-line to 3-line noninverting clock driver and 1-line to 4-line
noninverting divide by 2 clock driver.

     Ŀ
 GND 1   24 OEQ
  Q1 2       23 Q3
  Q2 3       22 CLKQ
 GND 4       21 VCC
  X1 5       20 RST
 OEX 6   74  19 X3
CLKX 7  330  18 GND
  X2 8       17 X4
 GND 9       16 VCC
  Y1 10      15 OEY
  Y2 11      14 Y3
 GND 12      13 CLKY
     
#
743351
10-tap noninverting delay lines (20, 50 or 100ns total delay).

    Ŀ
  A 1   16 VCC
    2       15
    3       14 Y1
 Y2 4  743  13 Y3
 Y4 5  351  12 Y5
 Y6 6       11 Y7
 Y8 7       10 Y9
GND 8        9 Y10
    
#
74337
8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.

     Ŀ
  Y3 1   20 Y2
 GND 2       19 GND
  Y4 3       18 Y1
 VCC 4       17 VCC
 /OE 5   74  16 CLK
/RST 6  337  15 GND
 VCC 7       14 VCC
  Q1 8       13 Q4
 GND 9       12 GND
  Q2 10      11 Q3
     
#
74338
6-line noninverting clock driver with divide by 2 and PLL.
Four outputs toggle at the clock, one at one-half, one at double speed.

    Ŀ
GND 1   20 /OE
 Y1 2       19 VCC
GND 3       18 DF
 Y2 4       17 VCC
GND 5   74  16 CLKIN
GND 6  338  15 GND
 Y3 7       14 HF
GND 8       13 VCC
 Y4 9       12 /RST
GND 10      11 VCC
    
#
74339
8-line 3-state noninverting clock driver with divide by 2 output on 4 lines.

     Ŀ
  Y3 1   20 Y2
 GND 2       19 GND
  Y4 3       18 Y1
 VCC 4       17 VCC
 /OE 5   74  16 CLK
/RST 6  339  15 GND
 VCC 7       14 VCC
  Q1 8       13 Q4
 GND 9       12 GND
  Q2 10      11 Q3
     
#
74340
8-line inverting clock driver.

    Ŀ
VCC 1   20 VCC
 E1 2       19 Q1
 E2 3       18 Q2
 IN 4       17 GND
 P0 5   74  16 Q3
 P1 6  340  15 Q4
VCC 7       14 GND
 Q8 8       13 Q5
 Q7 9       12 Q6
GND 10      11 GND
    

#
74348
8-to-3 line 3-state inverting priority encoder with cascade inputs.

    Ŀ
/A4 1   16 VCC
/A5 2       15 /EO
/A6 3       14 /GS
/A7 4   74  13 /A3
/EI 5  348  12 /A2
 Y2 6       11 /A1
 Y1 7       10 /A0
GND 8        9 Y0
    
#
74352
8-to-2 line inverting data selector/multiplexer with separate enables.

     Ŀ
/1EN 1   16 VCC
  S1 2       15 /2EN
 1A3 3       14 S0
 1A2 4   74  13 2A3
 1A1 5  352  12 2A2
 1A0 6       11 2A1
  1Y 7       10 2A0
 GND 8        9 2Y
     
#
74353
8-to-2 line 3-state inverting data selector/multiplexer.

     Ŀ
/1EN 1   16 VCC
  S1 2       15 /2EN
 1A3 3       14 S0
 1A2 4   74  13 2A3
 1A1 5  353  12 2A2
 1A0 6       11 2A1
 /1Y 7       10 2A0
 GND 8        9 /2Y
     
#
74354
8-to-1 line 3-state data selector/multiplexer with address and data latches
and complementary outputs.

    Ŀ
 A7 1   20 VCC
 A6 2       19 Y
 A5 3       18 /Y
 A4 4       17 OE3
 A3 5  74   16 /OE2
 A2 6  354  15 /OE1
 A1 7       14 A0
 A0 8       13 A1
DLE 9       12 A2
GND 10      11 ALE
    
#
74356
8-to-1 line 3-state data selector/multiplexer with address latch and data
register and complementary outputs.

    Ŀ
 A7 1   20 VCC
 A6 2       19 Y
 A5 3       18 /Y
 A4 4       17 OE3
 A3 5  74   16 /OE2
 A2 6  356  15 /OE1
 A1 7       14 A0
 A0 8       13 A1
DLE 9       12 A2
GND 10      11 ALE
    
#
74365
6-bit 3-state noninverting buffer/line driver.

     Ŀ            Ŀ
/OE1 1   16 VCC        /OE A  Y 
  A1 2       15 /OE2       ͵
  Y1 3       14 A6          1  X  Z 
  A2 4   74  13 Y6          0  0  0 
  Y2 5  365  12 A5          0  1  1 
  A3 6       11 Y5         
  Y3 7       10 A4
 GND 8        9 Y4
     
#
74366
6-bit 3-state inverting buffer/line driver.

     Ŀ            Ŀ
/OE1 1   16 VCC        /OE A /Y 
  A1 2       15 /OE2       ͵
 /Y1 3       14 A6          1  X  Z 
  A2 4   74  13 /Y6         0  0  1 
 /Y2 5  366  12 A5          0  1  0 
  A3 6       11 /Y5        
 /Y3 7       10 A4
 GND 8        9 /Y4
     
#
74367
2/4-bit 3-state noninverting buffer/line driver.

     Ŀ            Ŀ
/1OE 1   16 VCC        /OE A  Y 
 1A1 2       15 /2OE       ͵
 1Y1 3       14 2A2         1  X  Z 
 1A2 4   74  13 2Y2         0  0  0 
 1Y2 5  367  12 2A1         0  1  1 
 1A3 6       11 2Y1        
 1Y3 7       10 1A4
 GND 8        9 1Y4
     
#
74368
2/4-bit 3-state inverting buffer/line driver.

     Ŀ            Ŀ
/1OE 1   16 VCC        /OE A /Y 
 1A1 2       15 /2OE       ͵
/1Y1 3       14 2A2         1  X  Z 
 1A2 4   74  13 /2Y2        0  0  1 
/1Y2 5  368  12 2A1         0  1  0 
 1A3 6       11 /2Y1       
/1Y3 7       10 1A4
 GND 8        9 /1Y4
     
#
7437
Quad 2-input NAND gates with buffered output.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  1 
 2A 4  7437 11 /4Y          0  1  1 
 2B 5       10 3B           1  0  1 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
74373
8-bit 3-state transparent latch.

    Ŀ             Ŀ
/OE 1   20 VCC         /OE LE D  Q 
 Q1 2       19 Q8          ͵
 D1 3       18 D8           1  X  X  Z 
 D2 4       17 D7           0  0  X  - 
 Q2 5   74  16 Q7           0  1  0  0 
 Q3 6  373  15 Q6           0  1  1  1 
 D3 7       14 D6          
 D4 8       13 D5
 Q4 9       12 Q5
GND 10      11 LE
    
#
74374
8-bit 3-state D flip-flop.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D  Q 
 Q1 2       19 Q8          ͵
 D1 3       18 D8           1  X  X  Z 
 D2 4       17 D7           0  /  0  0 
 Q2 5   74  16 Q7           0  /  1  1 
 Q3 6  374  15 Q6           0 !/  X  - 
 D3 7       14 D6          
 D4 8       13 D5
 Q4 9       12 Q5
GND 10      11 CLK
    
#
74375
Dual 2-bit transparent latches with complementary outputs.

     Ŀ
 1D1 1   16 VCC
/1Q1 2       15 2D1
 1Q1 3       14 /2Q1
 1LE 4   74  13 2Q1
 1Q2 5  375  12 2LE
/1Q2 6       11 2Q2
 1D2 7       10 /2Q2
 GND 8        9 2D2
     
#
74376
4-bit J-/K flip-flop with reset.

     Ŀ            Ŀ
/RST 1   16 VCC         J /K CLK/RST Q /Q 
  J1 2       15 J4         ͵
 /K1 3       14 /K4         X  X  X   0  0  1 
  Q1 4   74  13 Q4          0  0  /   1  0  1 
  Q2 5  376  12 Q3          0  1  /   1  -  - 
 /K2 6       11 /K3         1  0  /   1 /Q  Q 
  J2 7       10 J3          1  1  /   1  1  0 
 GND 8        9 CLK         X  X !/   1  -  - 
                 
#
74377
8-bit D flip-flop with clock enable.

       Ŀ          Ŀ
/CLKEN 1   20 VCC      /CENCLK D  Q 
    Q1 2       19 Q8       ͵
    D1 3       18 D8         1  X  X  - 
    D2 4       17 D7         0  /  0  0 
    Q2 5   74  16 Q7         0  /  1  1 
    Q3 6  377  15 Q6         0 !/  X  - 
    D3 7       14 D6       
    D4 8       13 D5
    Q4 9       12 Q5
   GND 10      11 CLK
       
#
74378
6-bit D flip-flop with clock enable.

       Ŀ          Ŀ
/CLKEN 1   16 VCC      /CENCLK D  Q 
    Q1 2       15 Q6       ͵
    D1 3       14 D6         1  X  X  - 
    D2 4   74  13 D5         0  /  0  0 
    Q2 5  378  12 Q5         0  /  1  1 
    D3 6       11 D4         0 !/  X  - 
    Q3 7       10 Q4       
   GND 8        9 CLK
       
#
74379
6-bit D flip-flop with clock enable and complementary outputs.

       Ŀ          Ŀ
/CLKEN 1   16 VCC      /CENCLK D  Q /Q 
    Q1 2       15 Q4       ͵
   /Q1 3       14 /Q4        1  X  X  -  - 
    D1 4   74  13 D4         0  /  0  0  1 
    D2 5  379  12 D3         0  /  1  1  0 
   /Q2 6       11 /Q3        0 !/  X  -  - 
    Q2 7       10 Q3       
   GND 8        9 CLK
       
#
7438
Quad 2-input open-collector NAND gates with buffered output.

    Ŀ             Ŀ           __
 1A 1   14 VCC          A  B /Y       /Y = AB
 1B 2       13 4B          ͵
/1Y 3       12 4A           0  0  Z 
 2A 4  7438 11 /4Y          0  1  Z 
 2B 5       10 3B           1  0  Z 
/2Y 6        9 3A           1  1  0 
GND 7        8 /3Y         
    
#
74381
4-bit 8-function arithmetic logic unit (ALU)

    Ŀ
 A1 1   20 VCC
 B1 2       19 A2
 A0 3       18 B2
 B0 4       17 A3
 S0 5   74  16 B3
 S1 6  381  15 CIN
 S2 7       14 /P
 F0 8       13 /G
 F1 9       12 F3
GND 10      11 F2
    
#
74382
4-bit 8-function arithmetic logic unit (ALU) with ripple carry and overflow
outputs.

    Ŀ
 A1 1   20 VCC
 B1 2       19 A2
 A0 3       18 B2
 B0 4       17 A3
 S0 5   74  16 B3
 S1 6  382  15 CIN
 S2 7       14 COUT
 F0 8       13 OVR
 F1 9       12 F3
GND 10      11 F2
    
#
74385
Quad serial adder/subtractor.
Contains four independent adder/subtractor elements with common clock and
carry reset.

      Ŀ
  CLK 1   20 VCC
   1 2       19 4
1S//A 3       18 4S//A
   1B 4       17 4B
   1A 5   74  16 4A
   2A 6  385  15 3A
   2B 7       14 3B
2S//A 8       13 3S//A
   2 9       12 3
  GND 10      11 RST
      
#
74386
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3  74   12 4A           0  0  0 
 2Y 4  386  11 4Y           0  1  1 
 2A 5       10 3Y           1  0  1 
 2B 6        9 3B           1  1  0 
GND 7        8 3A          
    
#
74390
Dual 4-bit asynchronous decade counters with separate /2 and /5 sections
and reset.

       Ŀ
/1CLK0 1   16 VCC
  1RST 2       15 /2CLK0
   1Q0 3       14 2RST
/1CLK1 4   74  13 2Q0
   1Q1 5  390  12 /2CLK1
   1Q2 6       11 2Q1
   1Q3 7       10 2Q2
   GND 8        9 2Q3
       
#
74393
Dual 4-bit asynchronous binary counters with reset.

      Ŀ
/1CLK 1   14 VCC
 1RST 2       13 /2CLK
  1Q0 3   74  12 2RST
  1Q1 4  393  11 2Q0
  1Q2 5       10 2Q1
  1Q3 6        9 2Q2
  GND 7        8 2Q3
      
#
74395
4-bit 3-state shift register with load and asynchronous reset.

      Ŀ
 /RST 1   16 VCC
   SA 2       15 QA
    A 3       14 QB
    B 4   74  13 QC
    C 5  395  12 QD
    D 6       11 QD'
LD//S 7       10 CLK
  GND 8        9 /OE
      
#
74398
8-to-4 line data selector/multiplexer with output registers and complementary
outputs.

    Ŀ
  S 1   20 VCC
 1Y 2       19 4Y
/1Y 3       18 /4Y
1A0 4       17 4A0
1A1 5   74  16 4A1
2A1 6  398  15 3A1
2A0 7       14 3A0
/2Y 8       13 /3Y
 2Y 9       12 3Y
GND 10      11 CLK
    
#
74399
8-to-4 line inverting data selector/multiplexer with output registers.

    Ŀ
  S 1   16 VCC
 1Y 2       15 4Y
1A0 3       14 4A0
1A1 4   74  13 4A1
2A1 5  399  12 3A1
2A0 6       11 3A0
 2Y 7       10 3Y
GND 8        9 CLK
    
#
7440
Dual 4-input NAND gates with buffered output.

    Ŀ             Ŀ        ____
 1A 1   14 VCC          A  B  C  D /Y    /Y = ABCD
 1B 2       13 2D          ͵
    3       12 2C           0  X  X  X  1 
 1C 4  7440 11              1  0  X  X  1 
 1D 5       10 2B           1  1  0  X  1 
/1Y 6        9 2A           1  1  1  0  1 
GND 7        8 /2Y          1  1  1  1  0 
                 
#
7442
1-of-10 inverting decoder/demultiplexer.

    Ŀ             Ŀ
/Y0 1   16 VCC          S3 S2 S1 S0/Y0/Y1.../Y9
/Y1 2       15 S0          ͵
/Y2 3       14 S1           0  0  0  0  0  1  1  1 
/Y3 4       13 S2           0  0  0  1  1  0  1  1 
/Y4 5  7442 12 S3           .  .  .  .  1  1  .  1 
/Y5 6       11 /Y9          1  0  0  1  1  1  1  0 
/Y6 7       10 /Y8          1  0  1  X  1  1  1  1 
GND 8        9 /Y7          1  1  X  X  1  1  1  1 
                 
#
74423
Dual retriggerable monostable multivibrator with overriding reset.
Cannot be triggered via reset input.

       Ŀ
  /1TR 1   16 VCC
   1TR 2       15 1RCext
 /1RST 3       14 1Cext
   /1Q 4   74  13 1Q
    2Q 5  423  12 /2Q
 2Cext 6       11 /2RST
2RCext 7       10 2TR
   GND 8        9 /2TR
       
#
744374
8-bit 3-state dual-ranking D flip flop.
Designed to prevent metastable conditions in data synchronization
applications in which setup and hold times may be violated.

    Ŀ
 Q1 1   20 D1
 Q2 2       19 D2
 Q3 3       18 D3
 Q4 4       17 D4
GND 5  744  16 VCC
 Q5 6  374  15 D5
 Q6 7       14 D6
 Q7 8       13 D7
 Q8 9       12 D8
/OE 10      11 CLK
    
#
74465
8-bit 3-state noninverting buffer/line driver.

     Ŀ
/OE1 1   20 VCC
  A1 2       19 /OE2
  Y1 3       18 A8
  A2 4       17 Y8
  Y2 5  74   16 A7
  A3 6  465  15 Y7
  Y3 7       14 A6
  A4 8       13 Y6
  Y4 9       12 A5
 GND 10      11 Y5
     
#
7447
BCD to 7-segment decoder with ripple blank input and output.

     Ŀ
  A1 1   16 VCC
  A2 2       15 /YF
 /LT 3       14 /YG
/RBO 4       13 /YA
/RBI 5  7447 12 /YB
  A3 6       11 /YC
  A0 7       10 /YD
 GND 8        9 /YE
     
#
74490
Dual 4-bit asynchronous decade counters with set(9) and reset.

      Ŀ
/1CLK 1   16 VCC
 1RST 2       15 /2CLK
  1QA 3       14 2RST
 1SET 4   74  13 2Q0
  1QB 5  490  12 2SET
  1QC 6       11 2Q1
  1QD 7       10 2Q2
  GND 8        9 2Q3
      
#
7451
2-wide 2-input and 2-wide 3-input AND-NOR gates.

    Ŀ                  _____________________
 1A 1   14 VCC        /1Y = (1A1B1C)+(1D1E1F)
 2A 2       13 1B
 2B 3       12 1C               _______________
 2C 4  7451 11 1D         /2Y = (2A2B)+(2C2D)
 2D 5       10 1E
/2Y 6        9 1F
GND 7        8 /1Y
    
#
74519
8-bit open-collector noninverting identity comparator with enable.

    Ŀ
/OE 1   20 VCC
 A0 2       19 A=B
 B0 3       18 B7
 A1 4       17 A7
 B1 5   74  16 B6
 A2 6  519  15 A6
 B2 7       14 B5
 A3 8       13 A5
 B3 9       12 B4
GND 10      11 A4
    
#
74520
8-bit inverting identity comparator with itegrated 20k pull-up resistors
and enable.

    Ŀ
/EN 1   20 VCC
 A0 2       19 A=B
 B0 3       18 B7
 A1 4       17 A7
 B1 5   74  16 B6
 A2 6  520  15 A6
 B2 7       14 B5
 A3 8       13 A5
 B3 9       12 B4
GND 10      11 A4
    
#
74521
8-bit inverting identity comparator with enable.

    Ŀ
/OE 1   20 VCC
 A0 2       19 A=B
 B0 3       18 B7
 A1 4       17 A7
 B1 5   74  16 B6
 A2 6  521  15 A6
 B2 7       14 B5
 A3 8       13 A5
 B3 9       12 B4
GND 10      11 A4
    
#
74533
8-bit 3-state inverting transparent latch.

    Ŀ             Ŀ
/OE 1   20 VCC         /OE LE D  Q 
/Q1 2       19 /Q8         ͵
 D1 3       18 D8           1  X  X  Z 
 D2 4       17 D7           0  0  X  - 
/Q2 5   74  16 /Q7          0  1  0  0 
/Q3 6  533  15 /Q6          0  1  1  1 
 D3 7       14 D6          
 D4 8       13 D5
/Q4 9       12 /Q5
GND 10      11 LE
    
#
74534
8-bit 3-state inverting D flip-flop.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D /Q 
/Q1 2       19 /Q8         ͵
 D1 3       18 D8           1  X  X  Z 
 D2 4       17 D7           0  /  0  1 
/Q2 5   74  16 /Q7          0  /  1  0 
/Q3 6  534  15 /Q6          0 !/  X  - 
 D3 7       14 D6          
 D4 8       13 D5
/Q4 9       12 /Q5
GND 10      11 CLK
    
#
7454
4-wide 2/3-input AND-NOR gate.

    Ŀ                 ___________________________
  A 1   14 VCC        /Y = (AB)+(CDE)+(FGH)+(JK)
  B 2       13 K
  C 3       12 J
  D 4  7454 11 H
  E 5       10 G
 /Y 6        9 F
GND 7        8
    
#
74540
8-bit 3-state inverting buffer/line driver.

     Ŀ
/OE1 1   20 VCC
  A1 2       19 /OE2
  A2 3       18 /Y1
  A3 4       17 /Y2
  A4 5   74  16 /Y3
  A5 6  540  15 /Y4
  A6 7       14 /Y5
  A7 8       13 /Y6
  A8 9       12 /Y7
 GND 10      11 /Y8
     
#
745400
11-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
  Y1 1   28 A1
  Y2 2       27 A2
  Y3 3       26 A3
  Y4 4       25 A4
  Y5 5       24 A5
  Y6 6       23 A6
 GND 7   74  22 VCC
 GND 8  5400 21 VCC
  Y7 9       20 A7
  Y8 10      19 A8
  Y9 11      18 A9
 Y10 12      17 A10
 Y11 13      16 A11
/OE1 14      15 /OE2
     
#
745401
11-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
 /Y1 1   28 A1
 /Y2 2       27 A2
 /Y3 3       26 A3
 /Y4 4       25 A4
 /Y5 5       24 A5
 /Y6 6       23 A6
 GND 7   74  22 VCC
 GND 8  5401 21 VCC
 /Y7 9       20 A7
 /Y8 10      19 A8
 /Y9 11      18 A9
/Y10 12      17 A10
/Y11 13      16 A11
/OE1 14      15 /OE2
     
#
745402
12-bit 3-state noninverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
  Y1 1   28 A1
  Y2 2       27 A2
  Y3 3       26 A3
  Y4 4       25 A4
  Y5 5       24 A5
  Y6 6       23 A6
 GND 7   74  22 A7
  Y7 8  5402 21 VCC
  Y8 9       20 A8
  Y9 10      19 A9
 Y10 11      18 A10
 Y11 12      17 A11
 Y12 13      16 A12
/OE1 14      15 /OE2
     
#
745403
12-bit 3-state inverting buffer/MOS driver with integrated 25 series
output resistors.

     Ŀ
 /Y1 1   28 A1
 /Y2 2       27 A2
 /Y3 3       26 A3
 /Y4 4       25 A4
 /Y5 5       24 A5
 /Y6 6       23 A6
 GND 7   74  22 A7
 /Y7 8  5402 21 VCC
 /Y8 9       20 A8
 /Y9 10      19 A9
/Y10 11      18 A10
/Y11 12      17 A11
/Y12 13      16 A12
/OE1 14      15 /OE2
     
#
74541
8-bit 3-state noninverting buffer/line driver.

     Ŀ
/OE1 1   20 VCC
  A1 2       19 /OE2
  A2 3       18 Y1
  A3 4       17 Y2
  A4 5   74  16 Y3
  A5 6  541  15 Y4
  A6 7       14 Y5
  A7 8       13 Y6
  A8 9       12 Y7
 GND 10      11 Y8
     
#
74543
8-bit 3-state noninverting registered transceiver.

      Ŀ
/LEBA 1   24 VCC
 /GBA 2       23 /CEBA
   A1 3       22 B1
   A2 4       21 B2
   A3 5       20 B3
   A4 6   74  19 B4
   A5 7  543  18 B5
   A6 8       17 B6
   A7 9       16 B7
   A8 10      15 B8
/CEAB 11      14 /LEAB
  GND 12      13 /GAB
      
#
74544
8-bit 3-state inverting registered transceiver.

      Ŀ
/LEBA 1   24 VCC
 /GBA 2       23 /CEBA
   A1 3       22 B1
   A2 4       21 B2
   A3 5       20 B3
   A4 6   74  19 B4
   A5 7  544  18 B5
   A6 8       17 B6
   A7 9       16 B7
   A8 10      15 B8
/CEAB 11      14 /LEAB
  GND 12      13 /GAB
      
#
7455
2-wide 4-input AND-NOR gate.

    Ŀ                 ___________________
  A 1   14 VCC        /Y = (ABCD)+(EFGH)
  B 2       13 H
  C 3       12 G
  D 4  7455 11 F
    5       10 E
    6        9
GND 7        8 /Y
    
#
7456
Frequency divider.
Can generate one second timing pulses from 50 Hz.
Two '56 devices may be interconnected to give frequency division of 2500 to 1,
625 to 1, 100 to 1, etc.
Features a reset pin that is common to all three counters.

     Ŀ
CLKB 1    8 QC
 VCC 2        7 QB
  QA 3  7456  6 RST
 GND 4        5 CLKA
     
#
74561
4-bit 3-state synchronous binary counter with sync/async load, sync/async
reset, and ripple/clocked carry output.

      Ŀ
 /ALD 1   20 VCC
  CLK 2       19 RCO
   P0 3       18 CCO
   P1 4       17 /OE
   P2 5   74  16 Q0
   P3 6  561  15 Q1
  ENP 7       14 Q2
/ARST 8       13 Q3
/SRST 9       12 ENT
  GND 10      11 /SLD
      
#
74563
8-bit 3-state inverting transparent latch.

    Ŀ             Ŀ
/OE 1   20 VCC         /OE LE D /Q 
 D1 2       19 /Q1         ͵
 D2 3       18 /Q2          1  X  X  Z 
 D3 4       17 /Q3          0  0  X  - 
 D4 5   74  16 /Q4          0  1  0  1 
 D5 6  563  15 /Q5          0  1  1  0 
 D6 7       14 /Q6         
 D7 8       13 /Q7
 D8 9       12 /Q8
GND 10      11 LE
    
#
74564
8-bit 3-state inverting D flip-flop.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D /Q 
 D1 2       19 /Q1         ͵
 D2 3       18 /Q2          1  X  X  Z 
 D3 4       17 /Q3          0  /  0  1 
 D4 5   74  16 /Q4          0  /  1  0 
 D5 6  564  15 /Q5          0 !/  X  - 
 D6 7       14 /Q6         
 D7 8       13 /Q7
 D8 9       12 /Q8
GND 10      11 CLK
    
#
74568
4-bit 3-state synchronous decade up/down counter with load, sync/async reset,
and ripple/clocked carry output.

      Ŀ
 U//D 1   20 VCC
  CLK 2       19 /RCO
   P0 3       18 /CCO
   P1 4       17 /OE
   P2 5   74  16 Q0
   P3 6  568  15 Q1
 /ENP 7       14 Q2
/ARST 8       13 Q3
/SRST 9       12 /ENT
  GND 10      11 /LOAD
      
#
74569
4-bit 3-state synchronous binary up/down counter with load, sync/async reset,
and ripple/clocked carry output.

      Ŀ
 U//D 1   20 VCC
  CLK 2       19 /RCO
   P0 3       18 /CCO
   P1 4       17 /OE
   P2 5   74  16 Q0
   P3 6  569  15 Q1
 /ENP 7       14 Q2
/ARST 8       13 Q3
/SRST 9       12 /ENT
  GND 10      11 /LOAD
      
#
7457
Frequency divider.
Can generate one second timing pulses from 60 Hz.
Two '57 devices may be interconnected to give frequency division of 3600 to 1,
1800 to 1, 900 to 1, etc.
Features a reset pin that is common to all three counters.

     Ŀ
CLKB 1    8 QC
 VCC 2        7 QB
  QA 3  7457  6 RST
 GND 4        5 CLKA
     
#
74573
8-bit 3-state transparent latch.

    Ŀ             Ŀ
/OE 1   20 VCC         /OE LE D /Q 
 D1 2       19 Q1          ͵
 D2 3       18 Q2           1  X  X  Z 
 D3 4       17 Q3           0  0  X  - 
 D4 5   74  16 Q4           0  1  0  0 
 D5 6  573  15 Q5           0  1  1  1 
 D6 7       14 Q6          
 D7 8       13 Q7
 D8 9       12 Q8
GND 10      11 LE
    
#
74574
8-bit 3-state D flip-flop.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D  Q 
 D1 2       19 Q1          ͵
 D2 3       18 Q2           1  X  X  Z 
 D3 4       17 Q3           0  /  0  0 
 D4 5   74  16 Q4           0  /  1  1 
 D5 6  574  15 Q5           0 !/  X  - 
 D6 7       14 Q6          
 D7 8       13 Q7
 D8 9       12 Q8
GND 10      11 CLK
    
#
74575
8-bit 3-state D flip-flop with reset.

     Ŀ            Ŀ
/RST 1   24 VCC        /RST/OECLK D  Q 
 /OE 2       23            ͵
  D1 3       22 Q1           0  1  X  X  Z 
  D2 4       21 Q2           X  0  X  X  0 
  D3 5       20 Q3           1  0  /  0  0 
  D4 6   74  19 Q4           1  0  /  1  1 
  D5 7  575  18 Q5           1  0 !/  X  - 
  D6 8       17 Q6         
  D7 9       16 Q7
  D8 10      15 Q8
     11      14 CLK
 GND 12      13
     
#
74576
8-bit 3-state inverting D flip-flop.

    Ŀ             Ŀ
/OE 1   20 VCC         /OECLK D /Q 
 D1 2       19 /Q1         ͵
 D2 3       18 /Q2          1  X  X  Z 
 D3 4       17 /Q3          0  /  0  1 
 D4 5   74  16 /Q4          0  /  1  0 
 D5 6  576  15 /Q5          0 !/  X  - 
 D6 7       14 /Q6         
 D7 8       13 /Q7
 D8 9       12 /Q8
GND 10      11 CLK
    
#
74577
8-bit 3-state inverting D flip-flop with reset.

     Ŀ            Ŀ
/RST 1   24 VCC        /RST/OECLK D /Q 
 /OE 2       23            ͵
  D1 3       22 /Q1          0  1  X  X  Z 
  D2 4       21 /Q2          X  0  X  X  1 
  D3 5       20 /Q3          1  0  /  0  1 
  D4 6   74  19 /Q4          1  0  /  1  0 
  D5 7  577  18 /Q5          1  0 !/  X  - 
  D6 8       17 /Q6        
  D7 9       16 /Q7
  D8 10      15 /Q8
     11      14 CLK
 GND 12      13
     
#
7458
2-wide 2-input and 2-wide 3-input AND-OR gates.

    Ŀ
 1A 1   14 VCC         1Y = (1A1B1C)+(1D1E1F)
 2A 2       13 1B
 2B 3       12 1C
 2C 4  7458 11 1D          2Y = (2A2B)+(2C2D)
 2D 5       10 1E
 2Y 6        9 1F
GND 7        8 1Y
    
#
74580
8-bit 3-state inverting transparent latch.

    Ŀ             Ŀ
/OE 1   20 VCC         /OE LE D /Q 
 D1 2       19 /Q1         ͵
 D2 3       18 /Q2          1  X  X  Z 
 D3 4       17 /Q3          0  0  X  - 
 D4 5   74  16 /Q4          0  1  0  1 
 D5 6  580  15 /Q5          0  1  1  0 
 D6 7       14 /Q6         
 D7 8       13 /Q7
 D8 9       12 /Q8
GND 10      11 LE
    
#
74589
8-bit 3-state parallel-in serial-out shift register with input registers.
Independent clocks for shift and storage registers.

    Ŀ
  B 1   16 VCC
  C 2       15 A
  D 3       14 SA
  E 4   74  13 /SLD
  F 5  589  12 RCLK
  G 6       11 SCLK
  H 7       10 /OE
GND 8        9 QH
    
#
74590
8-bit 3-state synchronous binary counter with reset and output registers.
Separate clocks for both counter and storage register, ripple carry output.

    Ŀ
 Q1 1   16 VCC
 Q2 2       15 Q0
 Q3 3       14 /OE
 Q4 4   74  13 RCLK
 Q5 5  590  12 /CLKEN
 Q6 6       11 CCLK
 Q7 7       10 /CRST
GND 8        9 /RCO
    
#
74592
8-bit synchronous binary counter with input registers.
Separate clocks for counter and input register.  Counter outputs only
internally connected but ripple carry and clock outputs available.

    Ŀ
 P1 1   16 VCC
 P2 2       15 P0
 P3 3       14 /CLOAD
 P4 4   74  13 RCLK
 P5 5  592  12 /CLKEN
 P6 6       11 CCLK
 P7 7       10 /CRST
GND 8        9 /RCO
    
#
74593
8-bit 3-state synchronous binary counter with input registers and ripple
carry and clock outputs.  Separate clocks for counter and input registers.

     Ŀ
  P0 1   20 VCC
  P1 2       19 OE
  P2 3       18 /OE
  P3 4       17 /RCLKEN
  P4 5   74  16 RCLK
  P5 6  593  15 CLKEN
  P6 7       14 /CLKEN
  P7 8       13 CCLK
/CLD 9       12 /CRST
 GND 10      11 /RCO
     
#
74594
8-bit serial-in parallel-out shift register with output registers and
asynchronous reset.  Independent clocks and resets for shift and
storage registers.

    Ŀ
 QB 1   16 VCC
 QC 2       15 QA
 QD 3       14 SA
 QE 4   74  13 /RRST
 QF 5  594  12 RCLK
 QG 6       11 SCLK
 QH 7       10 /SRST
GND 8        9 QH'
    
#
74595
8-bit 3-state serial-in parallel-out shift register with output registers and
asynchronous reset.  Independent clocks for shift and storage registers.

    Ŀ
 QB 1   16 VCC
 QC 2       15 QA
 QD 3       14 SA
 QE 4   74  13 /OE
 QF 5  595  12 RCLK
 QG 6       11 SCLK
 QH 7       10 /SRST
GND 8        9 QH'
    
#
74596
8-bit open-collector serial-in parallel-out shift register with output
registers and asynchronous reset.  Independent clocks for shift and storage
registers.

    Ŀ
 QB 1   16 VCC
 QC 2       15 QA
 QD 3       14 SA
 QE 4   74  13 /OE
 QF 5  595  12 RCLK
 QG 6       11 SCLK
 QH 7       10 /SRST
GND 8        9 QH'
    
#
74597
8-bit parallel-in serial-out shift register with input registers and
asynchronous reset.  Independent clocks for shift and storage registers.

    Ŀ
  B 1   16 VCC
  C 2       15 A
  D 3       14 SA
  E 4   74  13 /SLD
  F 5  597  12 RCLK
  G 6       11 SCLK
  H 7       10 /SRST
GND 8        9 QH'
    
#
74598
8-bit 3-state shift register with input registers, asynchronous reset and
selectable serial input.  Independent clocks for shift and storage registers.

     Ŀ
  PA 1   20 VCC
  PB 2       19 DS
  PC 3       18 SA0
  PD 4       17 SA1
  PE 5   74  16 /OE
  PF 6  598  15 RCLK
  PG 7       14 /SCE
  PH 8       13 SCLK
/SLD 9       12 /SRST
 GND 10      11 QH'
     
#
74620
8-bit 3-state inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

    Ŀ
GAB 1   20 VCC
 A1 2       19 /GBA
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  620  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74621
8-bit open-collector noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

    Ŀ
GAB 1   20 VCC
 A1 2       19 /GBA
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  621  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74623
8-bit 3-state noninverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

    Ŀ
GAB 1   20 VCC
 A1 2       19 /GBA
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  623  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74638
8-bit 3-state/open-collector inverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ
DIR 1   20 VCC
 A1 2       19 /OE
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  638  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74639
8-bit 3-state/open-collector noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ
DIR 1   20 VCC
 A1 2       19 /OE
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  639  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74640
8-bit 3-state inverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ             Ŀ
DIR 1   20 VCC         /ENDIR A  B 
 A1 2       19 /EN         ͵
 A2 3       18 B1           1  X  Z  Z 
 A3 4       17 B2           0  0 /B  Z 
 A4 5  74   16 B3           0  1  Z /A 
 A5 6  640  15 B4          
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74641
8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ
DIR 1   20 VCC
 A1 2       19 /OE
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  641  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74642
8-bit open-collector inverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ
DIR 1   20 VCC
 A1 2       19 /OE
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  642  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74643
8-bit 3-state inverting/noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ             Ŀ
DIR 1   20 VCC         /ENDIR A  B 
 A1 2       19 /EN         ͵
 A2 3       18 B1           1  X  Z  Z 
 A3 4       17 B2           0  0  B  Z 
 A4 5  74   16 B3           0  1  Z /A 
 A5 6  643  15 B4          
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74645
8-bit 3-state noninverting bus transceiver.
Enable and direction pins control output enables.

    Ŀ
DIR 1   20 VCC
 A1 2       19 /OE
 A2 3       18 B1
 A3 4       17 B2
 A4 5  74   16 B3
 A5 6  642  15 B4
 A6 7       14 B5
 A7 8       13 B6
 A8 9       12 B7
GND 10      11 B8
    
#
74646
8-bit 3-state noninverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
DIR 3       22 SBA
 A1 4       21 /OE
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  646  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74648
8-bit 3-state inverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
DIR 3       22 SBA
 A1 4       21 /OE
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  648  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74651
8-bit 3-state inverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
GAB 3       22 SBA
 A1 4       21 /GBA
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  651  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74652
8-bit 3-state noninverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
GAB 3       22 SBA
 A1 4       21 /GBA
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  652  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74653
8-bit 3-state/open-collector inverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
GAB 3       22 SBA
 A1 4       21 /GBA
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  653  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74654
8-bit 3-state/open-collector noninverting registered transceiver.

    Ŀ
CAB 1   24 VCC
SAB 2       23 CBA
GAB 3       22 SBA
 A1 4       21 /GBA
 A2 5       20 B1
 A3 6   74  19 B2
 A4 7  654  18 B3
 A5 8       17 B4
 A6 9       16 B5
 A7 10      15 B6
 A8 11      14 B7
GND 12      13 B8
    
#
74657
8-bit 3-state noninverting bus transceiver with parity generator/checker.
Enable and direction pins control output enables.

       Ŀ
   DIR 1   24 /OE
    A1 2       23 B1
    A2 3       22 B2
    A3 4       21 B3
    A4 5       20 B4
    A5 6   74  19 GND
   VCC 7  657  18 GND
    A6 8       17 B5
    A7 9       16 B6
    A8 10      15 B7
  O//E 11      14 B8
/ERROR 12      13 PAR
       
#
74666
8-bit 3-state transparent latch with readback, set and reset.
(The Number of the Beast).

      Ŀ
/OERB 1   24 VCC
 /OE1 2       23 /OE2
   D1 3       22 Q1
   D2 4       21 Q2
   D3 5       20 Q3
   D4 6   74  19 Q4
   D5 7  666  18 Q5
   D6 8       17 Q6
   D7 9       16 Q7
   D8 10      15 Q8
 /RST 11      14 /SET
  GND 12      13 LE
      
#
74669
4-bit synchronous binary up/down counter with load and ripple carry output.

     Ŀ
U//D 1   16 VCC
 CLK 2       15 /RCO
  P0 3       14 Q0
  P1 4   74  13 Q1
  P2 5  169  12 Q2
  P3 6       11 Q3
/ENP 7       10 /ENT
 GND 8        9 /LOAD
     
#
74670
4x4-bit 3-state dual-port register file.

    Ŀ
 D2 1   16 VCC
 D3 2       15 D1
 D4 3       14 WA0
RA1 4   74  13 WA1
RA0 5  670  12 /WR
 Q4 6       11 /RD
 Q3 7       10 Q1
GND 8        9 Q2
    
#
74673
16-bit serial-in parallel-out shift register with output storage registers
and asynchronous reset.

      Ŀ
  /CS 1   24 VCC
 SCLK 2       23 Y15
 R//W 3       22 Y14
/STCL 4       21 Y13
M/SCL 5       20 Y12
S/Q15 6   74  19 Y11
   Y0 7  673  18 Y10
   Y1 8       17 Y9
   Y2 9       16 Y8
   Y3 10      15 Y7
   Y4 11      14 Y6
  GND 12      13 Y5
      
#
74674
16-bit parallel-in serial-out shift register.

      Ŀ
  /CS 1   24 VCC
 SCLK 2       23 Y15
 R//W 3       22 Y14
      4       21 Y13
 MODE 5       20 Y12
S/Q15 6   74  19 Y11
   Y0 7  673  18 Y10
   Y1 8       17 Y9
   Y2 9       16 Y8
   Y3 10      15 Y7
   Y4 11      14 Y6
  GND 12      13 Y5
      
#
74677
16-bit inverting address comparator with enable.

    Ŀ
 A1 1   24 VCC
 A2 2       23 /EN
 A3 3       22 Y
 A4 4       21 P3
 A5 5       20 P2
 A6 6   74  19 P1
 A7 7  677  18 P0
 A8 8       17 A16
 A9 9       16 A15
A10 10      15 A14
A11 11      14 A13
GND 12      13 A12
    
#
74682
8-bit inverting magnitude comparator with integrated 100k pull-up resistors.

     Ŀ
/A>B 1   20 VCC
  A0 2       19 A=B
  B0 3       18 B7
  A1 4       17 A7
  B1 5   74  16 B6
  A2 6  682  15 A6
  B2 7       14 B5
  A3 8       13 A5
  B3 9       12 B4
 GND 10      11 A4
     
#
74684
8-bit inverting magnitude comparator.

     Ŀ
/A>B 1   20 VCC
  A0 2       19 A=B
  B0 3       18 B7
  A1 4       17 A7
  B1 5   74  16 B6
  A2 6  684  15 A6
  B2 7       14 B5
  A3 8       13 A5
  B3 9       12 B4
 GND 10      11 A4
     
#
74686
8-bit inverting magnitude comparator with enable.

     Ŀ
/A>B 1   24 VCC
/EN1 2       23 /EN2
  A0 3       22 /A=B
  B0 4       21 B7
  A1 5       20 A7
  B1 6   74  19
     7  686  18 B6
  A2 8       17 A6
  B2 9       16 B5
  A3 10      15 A5
  B3 11      14 B4
 GND 12      13 A4
     
#
74687
8-bit open-collector inverting magnitude comparator with enable.

     Ŀ
/A>B 1   24 VCC
/EN1 2       23 /EN2
  A0 3       22 /A=B
  B0 4       21 B7
  A1 5       20 A7
  B1 6   74  19
     7  687  18 B6
  A2 8       17 A6
  B2 9       16 B5
  A3 10      15 A5
  B3 11      14 B4
 GND 12      13 A4
     
#
74688
8-bit inverting identity comparator with enable.

    Ŀ
/EN 1   20 VCC
 A0 2       19 A=B
 B0 3       18 B7
 A1 4       17 A7
 B1 5   74  16 B6
 A2 6  688  15 A6
 B2 7       14 B5
 A3 8       13 A5
 B3 9       12 B4
GND 10      11 A4
    
#
74689
8-bit open-collector inverting identity comparator with enable.

    Ŀ
/EN 1   20 VCC
 A0 2       19 A=B
 B0 3       18 B7
 A1 4       17 A7
 B1 5   74  16 B6
 A2 6  689  15 A6
 B2 7       14 B5
 A3 8       13 A5
 B3 9       12 B4
GND 10      11 A4
    
#
74691
4-bit 3-state synchronous binary counter with output registers, asynchronous
reset and ripple carry output.  Multiplexed register/counter outputs.

      Ŀ
/CRST 1   20 VCC
 CCLK 2       19 RCO
   P0 3       18 Q0
   P1 4       17 Q1
   P2 5   74  16 Q2
   P3 6  691  15 Q3
  ENP 7       14 ENT
/RRST 8       13 /LOAD
 RCLK 9       12 /OE
  GND 10      11 R//C
      
#
74697
4-bit 3-state synchronous binary up/down counter with output registers,
asynchronous reset and ripple carry output.  Multiplexed register/counter
outputs.

      Ŀ
 U//D 1   20 VCC
 CCLK 2       19 RCO
   P0 3       18 Q0
   P1 4       17 Q1
   P2 5   74  16 Q2
   P3 6  697  15 Q3
  ENP 7       14 ENT
/CRST 8       13 /LOAD
 RCLK 9       12 /OE
  GND 10      11 R//C
      
#
74699
4-bit 3-state synchronous binary up/down counter with output registers,
reset and ripple carry output.  Multiplexed register/counter
outputs.

      Ŀ
 U//D 1   20 VCC
 CCLK 2       19 RCO
   P0 3       18 Q0
   P1 4       17 Q1
   P2 5   74  16 Q2
   P3 6  699  15 Q3
  ENP 7       14 ENT
/CRST 8       13 /LOAD
 RCLK 9       12 /OE
  GND 10      11 R//C
      
#
747001
Quad 2-input AND gates with schmitt-trigger inputs.
0.8V typical input hysteresis at VCC=+5V.

    Ŀ             Ŀ
 1A 1   14 VCC          A  B  Y        Y = AB
 1B 2       13 4B          ͵
 1Y 3  747  12 4A           0  0  0 
 2A 4  001  11 4Y           0  1  0 
 2B 5       10 3B           1  0  0 
 2Y 6        9 3A           1  1  1 
GND 7        8 3Y          
    
#
7472
J-K flip-flop with triple ANDed J an K inputs, set and reset.

     Ŀ            Ŀ
     1   14 VCC        J1J2J3K1K2K3CLK/SET/RST Q /Q 
/RST 2       13 /SET       ͵
  J1 3       12 CLK            X       X    X   0   0  ?  ? 
  J2 4  7472 11 K3             X       X    X   0   1  1  0 
  J3 5       10 K2             X       X    X   1   0  0  1 
  /Q 6        9 K1             0       0    /   1   1  -  - 
 GND 7        8 Q              0       1    /   1   1  0  1 
                     1       0    /   1   1  1  0 
                                 1       1    /   1   1 /Q  Q 
                                 X       X   !/   1   1  -  - 
                             
#
747266
Quad 2-input XNOR gates.

    Ŀ             Ŀ           _ 
 1A 1   14 VCC          A  B /Y      /Y = A$B
 1B 2       13 4B          ͵
/1Y 3  747  12 4A           0  0  1 
 2A 4  266  11 /4Y          0  1  0 
 2B 5       10 3B           1  0  0 
/2Y 6        9 3A           1  1  1 
GND 7        8 /3Y         
    
#
7473
Dual negative-edge-triggered J-K flip-flop with reset.

      Ŀ           Ŀ
/1CLK 1   14 1J         J  K /CLK/RST Q /Q 
/1RST 2       13 /1Q       ͵
   1K 3       12 1Q         X  X   X   0  0  1 
  VCC 4  7473 11 GND        0  0   \   1  -  - 
/2CLK 5       10 2K         0  1   \   1  0  1 
/2RST 6        9 2Q         1  0   \   1  1  0 
   2J 7        8 /2Q        1  1   \   1 /Q  Q 
                  X  X  !\   1  -  - 
                             
#
7474
Dual D flip-flop with set and reset.

      Ŀ           Ŀ
/1RST 1   14 VCC        D CLK/SET/RST Q /Q 
   1D 2       13 /2RST     ͵
 1CLK 3       12 2D         X  X   0   0  1  1 
/1SET 4  7474 11 2CLK       X  X   0   1  1  0 
   1Q 5       10 /2SET      X  X   1   0  0  1 
  /1Q 6        9 2Q         0  /   1   1  0  1 
  GND 7        8 /2Q        1  /   1   1  1  1 
                  X !/   1   1  -  - 
                             
#
7475
Dual 2-bit transparent latches with complementary outputs.

     Ŀ
/1Q1 1   16 1Q1
 1D1 2       15 1Q2
 1D2 3       14 /1Q2
 2LE 4       13 1LE
 VCC 5  7475 12 GND
 2D1 6       11 /2Q1
 2D2 7       10 2Q1
/2Q2 8        9 2Q2
     
#
74756
Dual 4-bit open-collector inverting buffer/line driver.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
/2Y4 3       18 /1Y1
 1A2 4       17 2A4
/2Y3 5  74   16 /1Y2
 1A3 6  756  15 2A3
/2Y2 7       14 /1Y3
 1A4 8       13 2A2
/2Y1 9       12 /1Y4
 GND 10      11 2A1
     
#
74757
Dual 4-bit open-collector noninverting buffer/line driver.
One active low, one active high output enable.

     Ŀ
/1OE 1   20 VCC
 1A4 2       19 2OE
 2Y1 3       18 1Y1
 1A3 4       17 2A4
 2Y2 5  74   16 1Y2
 1A2 6  757  15 2A3
 2Y3 7       14 1Y3
 1A1 8       13 2A2
 2Y4 9       12 1Y4
 GND 10      11 2A1
     
#
74758
4-bit open-collector inverting bus transceiver.
Two enable pins control output enables, one active high and one active low.

     Ŀ
/GAB 1   14 VCC
     2       13 GBA
  A1 3  74   12
  A2 4  758  11 B1
  A3 5       10 B2
  A4 6        9 B3
 GND 7        8 B4
     
#
7476
Dual J-K flip-flops with set and reset.

      Ŀ           Ŀ
 1CLK 1   16 1K         J  K CLK/SET/RST Q /Q 
/1SET 2       15 1Q        ͵
/1RST 3       14 /1Q        X  X  X   0   0  0  0 
   1J 4       13 GND        X  X  X   0   1  1  0 
  VCC 5  7476 12 K          X  X  X   1   0  0  1 
 2CLK 6       11 2Q         0  0  /   1   1  -  - 
/2SET 7       10 /2Q        0  1  /   1   1  0  1 
/2RST 8        9 2J         1  0  /   1   1  1  0 
                  1  1  /   1   1 /Q  Q 
                              X  X !/   1   1  -  - 
                             
#
74760
Dual 4-bit open-collector noninverting buffer/line driver.

     Ŀ
/1OE 1   20 VCC
 1A1 2       19 /2OE
 2Y4 3       18 1Y1
 1A2 4       17 2A4
 2Y3 5  74   16 1Y2
 1A3 6  760  15 2A3
 2Y2 7       14 1Y3
 1A4 8       13 2A2
 2Y1 9       12 1Y4
 GND 10      11 2A1
     
#
7478
Dual negative-edge-triggered J-K flip-flops with common clock, set and
common reset.

      Ŀ           Ŀ
 /CLK 1   14 1K         J  K /CLK/SET/RST Q /Q 
/1SET 2       13 1Q        ͵
   1J 3       12 /1Q        X  X   X   0   0  ?  ? 
  VCC 4  7478 11 GND        X  X   X   0   1  1  0 
 /RST 5       10 2J         X  X   X   1   0  0  1 
/2SET 6        9 /2Q        0  0   \   1   1  -  - 
   2K 7        8 2Q         0  1   \   1   1  0  1 
                  1  0   \   1   1  1  0 
                              1  1   \   1   1 /Q  Q 
                              X  X  !\   1   1  -  - 
                             
#
748003
Dual 2-input NAND gates.

    Ŀ                 __
 1A 1    8 VCC        /Y = AB
 1B 2  748   7 2B
/1Y 3  003   6 2A
GND 4        5 /2Y
    

#
74804
Hex 2-input NAND gates/line drivers.

    Ŀ             Ŀ           __
 1A 1   20 VCC          A  B /Y       /Y = AB
 1B 2       19 6B          ͵
/1Y 3       18 6A           0  0  1 
 2A 4       17 /6Y          0  1  1 
 2B 5   74  16 5B           1  0  1 
/2Y 6  804  15 5A           1  1  0 
 3A 7       14 /5Y         
 3B 8       13 4B
/3Y 9       12 4A
GND 10      11 /4Y
    
#
74805
Hex 2-input NOR gates/line drivers.

    Ŀ             Ŀ           ___
 1A 1   20 VCC          A  B /Y       /Y = A+B
 1B 2       19 6B          ͵
/1Y 3       18 6A           0  0  1 
 2A 4       17 /6Y          0  1  0 
 2B 5   74  16 5B           1  0  0 
/2Y 6  805  15 5A           1  1  0 
 3A 7       14 /5Y         
 3B 8       13 4B
/3Y 9       12 4A
GND 10      11 /4Y
    
#
74808
Hex 2-input AND gates/line drivers.

    Ŀ             Ŀ
 1A 1   20 VCC          A  B  Y        Y = AB
 1B 2       19 6B          ͵
 1Y 3       18 6A           0  0  0 
 2A 4       17 6Y           0  1  0 
 2B 5   74  16 5B           1  0  0 
 2Y 6  808  15 5A           1  1  1 
 3A 7       14 5Y          
 3B 8       13 4B
 3Y 9       12 4A
GND 10      11 4Y
    
#
74821
10-bit 3-state D flip-flop/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OECLK D  Q 
 D1 2       23 Q1          ͵
 D2 3       22 Q2           1  X  X  Z 
 D3 4       21 Q3           0  /  0  0 
 D4 5       20 Q4           0  /  1  1 
 D5 6   74  19 Q5           0 !/  X  - 
 D6 7  821  18 Q6          
 D7 8       17 Q7
 D8 9       16 Q8
 D9 10      15 Q9
D10 11      14 Q10
GND 12      13 CLK
    
#
74822
10-bit 3-state inverting D flip-flop/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OECLK D /Q 
 D1 2       23 /Q1         ͵
 D2 3       22 /Q2          1  X  X  Z 
 D3 4       21 /Q3          0  /  0  1 
 D4 5       20 /Q4          0  /  1  0 
 D5 6   74  19 /Q5          0 !/  X  - 
 D6 7  822  18 /Q6         
 D7 8       17 /Q7
 D8 9       16 /Q8
 D9 10      15 /Q9
D10 11      14 /Q10
GND 12      13 CLK
    
#
74823
9-bit 3-state D flip-flop/bus driver with clock enable and reset.

     Ŀ
 /OE 1   24 VCC
  D1 2       23 Q1
  D2 3       22 Q2
  D3 4       21 Q3
  D4 5       20 Q4
  D5 6   74  19 Q5
  D6 7  823  18 Q6
  D7 8       17 Q7
  D8 9       16 Q8
  D9 10      15 Q9
/RST 11      14 /CLKEN
 GND 12      13 CLK
     
#
74825
8-bit 3-state D flip-flop/bus driver with three output enables, clock enable
and reset.

     Ŀ
/OE1 1   24 VCC
/OE2 2       23 /OE3
  D1 3       22 Q1
  D2 4       21 Q2
  D3 5       20 Q3
  D4 6   74  19 Q4
  D5 7  825  18 Q5
  D6 8       17 Q6
  D7 9       16 Q7
  D8 10      15 Q8
/RST 11      14 /CLKEN
 GND 12      13 CLK
     
#
74827
10-bit 3-state noninverting buffer/line driver.

     Ŀ
/OE1 1   24 VCC
  A1 2       23 Y1
  A2 3       22 Y2
  A3 4       21 Y3
  A4 5       20 Y4
  A5 6  742  19 Y5
  A6 7  827  18 Y6
  A7 8       17 Y7
  A8 9       16 Y8
  A9 10      15 Y9
 A10 11      14 Y10
 GND 12      13 /OE2
     
#
7483
4-bit binary full adder with fast carry.

    Ŀ
 A4 1   16 B4          =A+B+CIN
 3 2       15 4
 A3 3       14 COUT
 B3 4       13 CIN
VCC 5  7483 12 GND
 2 6       11 B1
 B2 7       10 A1
 A2 8        9 1
    
#
74832
Hex 2-input OR gates/line drivers.

    Ŀ             Ŀ
 1A 1   20 VCC          A  B  Y        Y = A+B
 1B 2       19 6B          ͵
 1Y 3       18 6A           0  0  0 
 2A 4       17 6Y           0  1  1 
 2B 5   74  16 5B           1  0  1 
 2Y 6  832  15 5A           1  1  1 
 3A 7       14 5Y          
 3B 8       13 4B
 3Y 9       12 4A
GND 10      11 4Y
    
#
74833
8-bit 3-state noninverting bus transceiver with parity generator/checker
and parity register.

       Ŀ
  /OEA 1   24 VCC
    A1 2       23 B1
    A2 3       22 B2
    A3 4       21 B3
    A4 5       20 B4
    A5 6   74  19 B5
    A6 7  833  18 B6
    A7 8       17 B7
    A8 9       16 B8
/ERROR 10      15 PAR
  /CLR 11      14 /OEB
   GND 12      13 CLK
       
#
74841
10-bit 3-state transparent latch/bus driver.

    Ŀ             Ŀ
/OE 1   24 VCC         /OE LE D  Q 
 D1 2       23 Q1          ͵
 D2 3       22 Q2           1  X  X  Z 
 D3 4       21 Q3           0  0  X  - 
 D4 5       20 Q4           0  1  0  0 
 D5 6   74  19 Q5           0  1  1  1 
 D6 7  841  18 Q6          
 D7 8       17 Q7
 D8 9       16 Q8
 D9 10      15 Q9
D10 11      14 Q10
GND 12      13 LE
    
#
74843
9-bit 3-state transparent latch/bus driver with set and reset.

     Ŀ            Ŀ
 /OE 1   24 VCC        /RST/SET/OE LE D  Q 
  D1 2       23 Q1         ͵
  D2 3       22 Q2           0   1  0  X  X  0 
  D3 4       21 Q3           1   0  0  X  X  0 
  D4 5       20 Q4           X   X  1  X  X  Z 
  D5 6   74  19 Q5           1   1  0  0  X  - 
  D6 7  843  18 Q6           1   1  0  1  0  0 
  D7 8       17 Q7           1   1  0  1  1  1 
  D8 9       16 Q8         
  D9 10      15 Q9
/RST 11      14 /SET
 GND 12      13 LE
     
#
74845
8-bit 3-state transparent latch/bus driver with three output enables,
set and reset.

     Ŀ
/OE1 1   24 VCC
/OE2 2       23 /OE3
  D1 3       22 Q1
  D2 4       21 Q2
  D3 5       20 Q3
  D4 6   74  19 Q4
  D5 7  845  18 Q5
  D6 8       17 Q6
  D7 9       16 Q7
  D8 10      15 Q8
/RST 11      14 /SET
 GND 12      13 LE
     
#
7485
4-bit noninverting magnitude comparator with cascade inputs.

     Ŀ
  B3 1   16 VCC
IA<B 2       15 A3
IA=B 3       14 B2
IA>B 4       13 A2
OA>B 5  7485 12 A1
OA=B 6       11 B1
OA<B 7       10 A0
 GND 8        9 B0
     
#
74857
12-to-6 line inverting/noninverting data selector/multiplexer with masking
and zero detect.

      Ŀ
   S0 1   24 VCC
  1A0 2       23 S1
  1A1 3       22 6A0
   1Y 4       21 6A1
  2A0 5       20 6Y
  2A1 6   74  19 5A0
   2Y 7  857  18 5A1
  3A0 8       17 5Y
  3A1 9       16 4A0
   3Y 10      15 4A1
   ZD 11      14 4Y
  GND 12      13 COMP
      
#
7486
Quad 2-input XOR gates.

    Ŀ             Ŀ                    _   _
 1A 1   14 VCC          A  B  Y        Y = A$B = (AB)+(AB)
 1B 2       13 4B          ͵
 1Y 3       12 4A           0  0  0 
 2A 4  7486 11 4Y           0  1  1 
 2B 5       10 3B           1  0  1 
 2Y 6        9 3A           1  1  0 
GND 7        8 3Y          
    
#
74861
10-bit 3-state noninverting bus transceiver.

     Ŀ
/GBA 1   24 VCC
  A1 2       23 B1
  A2 3       22 B2
  A3 4       21 B3
  A4 5       20 B4
  A5 6   74  19 B5
  A6 7  861  18 B6
  A7 8       17 B7
  A8 9       16 B8
  A9 10      15 B9
 A10 11      14 B10
 GND 12      13 /GAB
     
#
74863
9-bit 3-state noninverting bus transceiver.

      Ŀ
/GBA1 1   24 VCC
   A1 2       23 B1
   A2 3       22 B2
   A3 4       21 B3
   A4 5       20 B4
   A5 6   74  19 B5
   A6 7  863  18 B6
   A7 8       17 B7
   A8 9       16 B8
   A9 10      15 B9
/GBA2 11      14 /GAB2
  GND 12      13 /GAB1
      
#
74867
8-bit synchronous binary up/down counter with load, asynchronous reset and
ripple carry output.

     Ŀ
  S0 1   24 VCC
  S1 2       23 /ENP
  P0 3       22 Q0
  P1 4       21 Q1
  P2 5       20 Q2
  P3 6   74  19 Q3
  P4 7  867  18 Q4
  P5 8       17 Q5
  P6 9       16 Q6
  P7 10      15 Q7
/ENT 11      14 CLK
 GND 12      13 /RCO
     
#
74869
8-bit synchronous binary up/down counter with load, reset and ripple carry
output.

     Ŀ
  S0 1   24 VCC
  S1 2       23 /ENP
  P0 3       22 Q0
  P1 4       21 Q1
  P2 5       20 Q2
  P3 6   74  19 Q3
  P4 7  869  18 Q4
  P5 8       17 Q5
  P6 9       16 Q6
  P7 10      15 Q7
/ENT 11      14 CLK
 GND 12      13 /RCO
     
#
74873
Dual 4-bit 3-state transparent latch with reset.

      Ŀ
/1RST 1   24 VCC
 /1OE 2       23 1LE
  1D1 3       22 1Q1
  1D2 4       21 1Q2
  1D3 5       20 1Q3
  1D4 6   74  19 1Q4
  2D1 7  873  18 2Q1
  2D2 8       17 2Q2
  2D3 9       16 2Q3
  2D4 10      15 2Q4
 /2OE 11      14 2LE
  GND 12      13 /2RST
      
#
74874
Dual 4-bit 3-state D flip-flops with reset.

      Ŀ           Ŀ
/1RST 1   24 VCC       /RST/OECLK D  Q 
 /1OE 2       23 1CLK      ͵
  1D1 3       22 1Q1         0  1  X  X  Z 
  1D2 4       21 1Q2         X  0  X  X  0 
  1D3 5       20 1Q3         1  0  /  0  0 
  1D4 6   74  19 1Q4         1  0  /  1  1 
  2D1 7  874  18 2Q1         1  0 !/  X  - 
  2D2 8       17 2Q2       
  2D3 9       16 2Q3
  2D4 10      15 2Q4
 /2OE 11      14 2CLK
  GND 12      13 /2RST
      
#
74878
Dual 4-bit 3-state D flip-flops with reset.

      Ŀ           Ŀ
/1RST 1   24 VCC       /RST/OECLK D  Q 
 /1OE 2       23 1CLK      ͵
  1D1 3       22 1Q1         0  1  X  X  Z 
  1D2 4       21 1Q2         X  0  X  X  0 
  1D3 5       20 1Q3         1  0  /  0  0 
  1D4 6   74  19 1Q4         1  0  /  1  1 
  2D1 7  878  18 2Q1         1  0 !/  X  - 
  2D2 8       17 2Q2       
  2D3 9       16 2Q3
  2D4 10      15 2Q4
 /2OE 11      14 2CLK
  GND 12      13 /2RST
      
#
74881
4-bit 16-function arithmetic logic unit (ALU)

    Ŀ
/B0 1   24 VCC
/A0 2       23 /A1
 S3 3       22 /B1
 S2 4       21 /A2
 S1 5       20 /B2
 S0 6   74  19 /A3
CIN 7  881  18 /B3
  M 8       17 /G
/F0 9       16 COUT
/F1 10      15 /P
/F2 11      14 A=B
GND 12      13 /F3
    
#
74885
8-bit noninverting magnitude comparator with cascade inputs and latchable
A inputs.

     Ŀ
L+/A 1   24 VCC
IA<B 2       23 ALE
IA>B 3       22 A7
  B7 4       21 A6
  B6 5       20 A5
  B5 6   74  19 A4
  B4 7  885  18 A3
  B3 8       17 A2
  B2 9       16 A1
  B1 10      15 A0
  B0 11      14 OA<B
 GND 12      13 OA>B
     
#
74899
8-bit 3-state noninverting latchable bus transceiver with parity
generator/checker and independent latch-enable inputs.

      Ŀ
 O//E 1   28 VCC
/ERRA 2       27 /OEAB
 LEAB 3       26 B1
   A1 4       25 B2
   A2 5       24 B3
   A3 6       23 B4
   A4 7   74  22 B5
   A5 8  899  21 B6
   A6 9       20 B7
   A7 10      19 B8
   A8 11      18 BPAR
 APAR 12      17 LEBA
/OEBA 13      16 /SEL
  GND 14      15 /ERRB
      
#
7490
4-bit asynchronous decade counter with /2 and /5 sections, set(9) and reset.

      Ŀ
/CLK1 1   14 /CLK0
 RST1 2       13
 RST2 3       12 Q0
      4  7490 11 Q3
  VCC 5       10 GND
 SET1 6        9 Q1
 SET2 7        8 Q2
      
#
7491
8-bit serial-in serial-out shift register with gated serial inputs and
complementary outputs.

    Ŀ
    1   14 /QH
    2       13 QH
    3       12 A
    4  7491 11 B
VCC 5       10 GND
    6        9 CLK
    7        8
    
#
7492
4-bit asynchronous divide-by-twelve counter with /2 and /6 sections and reset.

      Ŀ
/CLK1 1   14 /CLK0
      2       13
      3       12 Q0
      4  7492 11 Q3
  VCC 5       10 GND
 RST1 6        9 Q1
 RST2 7        8 Q2
      
#
7493
4-bit asynchronous binary counter with /2 and /8 sections and reset.

      Ŀ
/CLK1 1   14 /CLK0
 RST1 2       13
 RST2 3       12 Q0
      4  7493 11 Q3
  VCC 5       10 GND
      6        9 Q1
      7        8 Q2
      
#
7495
4-bit shift register with separate shift and parallel-load clocks.

      Ŀ
   SA 1   14 VCC
    A 2       13 QA
    B 3       12 QB
    C 4  7495 11 QC
    D 5       10 QD
L//SH 6        9 SHCLK
  GND 7        8 LDCLK
      
#
74956
8-bit 3-state noninverting latched transceiver.

     Ŀ
LEAB 1   24 VCC
 SAB 2       23 LEBA
 DIR 3       22 SBA
  A1 4       21 /OE
  A2 5       20 B1
  A3 6   74  19 B2
  A4 7  956  18 B3
  A5 8       17 B4
  A6 9       16 B5
  A7 10      15 B6
  A8 11      14 B7
 GND 12      13 B8
     
#
7496
5-bit shift register with asynchronous reset and load.

    Ŀ
CLK 1   16 /RST
  A 2       15 QA
  B 3       14 QB
  C 4       13 QC
VCC 5  7496 12 GND
  D 6       11 QD
  E 7       10 QE
 PE 8        9 SA
    
#
7497
6-bit synchronous binary rate multiplier.
Can perform fixed-rate or variable-rate frequency division.
Output frequency is equal to input frequency multiplied by the rate input M
and divided by 64.

      Ŀ
   B1 1   16 VCC
   B4 2       15 B3
   B5 3       14 B2
   B0 4       13 RST
    Z 5  7497 12 U/CAS
    Y 6       11 ENin
ENout 7       10 STRB
  GND 8        9 CLK
      
#
74990
8-bit transparent latch with readback.

      Ŀ
/OERB 1   20 VCC
   D1 2       19 Q1
   D2 3       18 Q2
   D3 4       17 Q3
   D4 5   74  16 Q4
   D5 6  990  15 Q5
   D6 7       14 Q6
   D7 8       13 Q7
   D8 9       12 Q8
  GND 10      11 LE
      
#
74992
9-bit 3-state transparent latch with readback and reset.

      Ŀ
/OERB 1   24 VCC
   D1 2       23 Q1
   D2 3       22 Q2
   D3 4       21 Q3
   D4 5       20 Q4
   D5 6   74  19 Q5
   D6 7  992  18 Q6
   D7 8       17 Q7
   D8 9       16 Q8
   D9 10      15 Q9
 /RST 11      14 /OE
  GND 12      13 LE
      
#
74994
10-bit transparent latch with readback.

      Ŀ
/OERB 1   24 VCC
   D1 2       23 Q1
   D2 3       22 Q2
   D3 4       21 Q3
   D4 5       20 Q4
   D5 6   74  19 Q5
   D6 7  994  18 Q6
   D7 8       17 Q7
   D8 9       16 Q8
   D9 10      15 Q9
  D10 11      14 Q10
  GND 12      13 LE
      
#
75173, LTC488
Quad RS485 line receiver.
Note the unusual ORed output enables.

    Ŀ             Ŀ
 B1 1   16 VCC           A-B   OE/OE Y 
 A1 2       15 B4          ͵
 Y1 3       14 A4          >+200mV 1  X  1 
 OE 4       13 Y4          >+200mV X  0  1 
 Y2 5 75173 12 /OE         <-200mV 1  X  0 
 A2 6       11 Y3          <-200mV X  0  0 
 B2 7       10 A3             X    0  1  Z 
GND 8        9 B3          
    
#
75174, LTC485
Quad RS485 line driver.

     Ŀ            Ŀ
 1A1 1   16 VCC         A  EN Y /Y 
 1Y1 2       15 2A2        ͵
/1Y1 3       14 2Y2         0  1  0  1 
 1EN 4       13 /2Y2        1  1  1  0 
/1Y2 5 75174 12 2EN         X  0  Z  Z 
 1Y2 6       11 /2Y1       
 1A2 7       10 2Y1
 GND 8        9 2A1
     
#
75175, LTC489
Quad RS485 line receiver.

    Ŀ             Ŀ
1B1 1   16 VCC           A-B   OE Y 
1A1 2       15 2B2         ͵
1Y1 3       14 2A2         >+200mV 1  1 
1OE 4       13 2Y2         <-200mV 1  0 
1Y2 5 75175 12 2OE            X    0  Z 
1A2 6       11 2Y1         
1B2 7       10 2A1
GND 8        9 2B1
    
#
75176, LTC485
RS485 line transceiver.
                             Receiver:           Transmitter:
    Ŀ             Ŀ   Ŀ
  Y 1    8 VCC           A-B  /OE Y     D DEN A  B 
/OE 2        7 B           ͵   ͵
DEN 3  75176 6 A           >+200mV 0  1     0  1  0  1 
  D 4        5 GND         <-200mV 0  0     1  1  1  0 
                    X    1  Z     X  0  Z  Z 
                                
#
765
Floppy disk controller.

       Ŀ
   RST 1       40 VCC
   /RD 2           39 /RW SEEK
   /WR 3           38 LCT DIR
   /CE 4           37 FR  STEP
D/S A0 5           36 HDL
    D0 6           35 RDY
    D1 7           34 WP  TS
    D2 8           33 FLT TR00
    D3 9           32 PS0
    D4 10   765    31 PS1
    D5 11   FDC    30 WDA
    D6 12          29 US0
    D7 13          28 US1
   DRQ 14          27 HD
 /DACK 15          26 MFM
    TC 16          25 WE
   IDX 17          24 VCO SYNC
   INT 18          23 RDD
   CLK 19          22 RDW
   GND 20          21 WCLK
       
#
78Hxx, 78H05, 78H12, 78H15, 78H24
Fixed voltage 5A positive power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
Ŀ2
͵
 
    1: Vin
      2: GND
      3: Vout
1 2 3
#
78Lxx, 78L05, 78L06, 78L07, 78L08, 78L09, 78L10, 78L12, 78L15, 78L24
Fixed voltage 100mA positive power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 92
ķ
 
½    1: Vin
      2: GND
      3: Vout
1 2 3
#
78Txx, 78T05, 78T12, 78T15, 78T24
Fixed voltage 3A positive power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
Ŀ2
͵
 
    1: Vin
      2: GND
      3: Vout
1 2 3
#
78xx, 7805, 7806, 7807, 7808, 7809, 7810, 7812, 7815, 7824
Fixed voltage 1A positive power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed 40V.

TO 220
Ŀ2
͵
 
    1: Vin
      2: GND
      3: Vout
1 2 3
#
79Lxx, 79L05, 79L06, 79L07, 79L08, 79L09, 79L10, 79L12, 79L15, 79L24
Fixed voltage 100mA negative power supply regulator.
Vin must exceed Vout by at least 3V, but may not exceed -40V.

TO 92
ķ
 
½    1: GND
      2: Vin
      3: Vout
1 2 3
#
79xx, 7905, 7906, 7907, 7908, 7909, 7910, 7912, 7915, 7924
Fixed voltage 1A negative power supply regulator
Vin must exceed Vout by at least 3V, but may not exceed -40V.

TO 220
Ŀ2
͵
 
    1: GND
      2: Vin
      3: Vout
1 2 3
#
8048, 8049, 8050, 8748, 8749, 8035, 8039, 8040 (DIP)
Intel 8048-series microcontroller.

      Ŀ
   T0 1       40 VCC
   X1 2           39 T1
   X0 3           38 P2.7
 /RST 4           37 P2.6
  /SS 5           36 P2.5
 /INT 6           35 P2.4
   EA 7           34 P1.7
  /RD 8           33 P1.6
/PSEN 9           32 P1.5
  /WR 10   8048   31 P1.4
  ALE 11  series  30 P1.3
  DB0 12          29 P1.2
  DB1 13          28 P1.1
  DB2 14          27 P1.0
  DB3 15          26 VCC_RAM VPP
  DB4 16          25 PROG
  DB5 17          24 P2.3
  DB6 18          23 P2.2
  DB7 19          22 P2.1
  GND 20          21 P2.0
      
#
8048, 8049, 8050, 8748, 8749, 8035, 8039, 8040 (PLCC)
Intel 8048-series microcontroller.

PLCC44
Ŀ
  7 /INT        18 DB4         29 VCCRAM VPP  40 P2.5       
  8 EA          19 DB5         30 P1.0        41 P2.6       
  9 /RD         20 DB6         31 P1.1        42 P2.7       
 10 /PSEN       21 DB7         32 P1.2        43 T1         
 11 /WR         22 GND         33 P1.3        44 VCC        
 12             23             34              1            
 13 ALE         24 P2.0        35 P1.4         2 T0         
 14 DB0         25 P2.1        36 P1.5         3 X1         
 15 DB1         26 P2.2        37 P1.6         4 X0         
 16 DB2         27 P2.3        38 P1.7         5 /RST       
 17 DB3         28 PROG        39 P2.4         6 /SS        

#
8051, 8052, 8054, 8058, 8751, 8752, 8754, 8758, 8031, 8032 (DIP)
Intel 8051-series microcontroller.

           Ŀ
   T2 P1.0 1       40 VCC
 T2EX P1.1 2           39 P0.0 AD0
  ECI P1.2 3           38 P0.1 AD1
 CEX0 P1.3 4           37 P0.2 AD2
 CEX1 P1.4 5           36 P0.3 AD3
 CEX2 P1.5 6           35 P0.4 AD4
 CEX3 P1.6 7           34 P0.5 AD5
 CEX4 P1.7 8           33 P0.6 AD6
       RST 9           32 P0.7 AD7
  RxD P3.0 10   8051   31 /EA VPP
  TxD P3.1 11  series  30 ALE /PROG
/INT0 P3.2 12          29 /PSEN
/INT1 P3.3 13          28 P2.7 A15
   T0 P3.4 14          27 P2.6 A14
   T1 P3.5 15          26 P2.5 A13
  /WR P3.6 16          25 P2.4 A12
  /RD P3.7 17          24 P2.3 A11
        X0 18          23 P2.2 A10
        X1 19          22 P2.1 A9
       GND 20          21 P2.0 A8
           
#
8051, 8052, 8054, 8058, 8751, 8752, 8754, 8758, 8031, 8032 (PLCC)
Intel 8051-series microcontroller.
The 8x54 and 8x58 have an extra GND pin.

PLCC44
Ŀ
  7 P1.5 CEX2   18 P3.6 /WR    29 P2.5 A13    40 P0.3 AD3   
  8 P1.6 CEX3   19 P3.7 /RD    30 P2.6 A14    41 P0.2 AD2   
  9 P1.7 CEX4   20 X0          31 P2.7 A15    42 P0.1 AD1   
 10 RST         21 X1          32 /PSEN       43 P0.0 AD0   
 11 P3.0 RxD    22 GND         33 ALE /PROG   44 VCC        
 12             23             34              1 (GND)      
 13 P3.1 TxD    24 P2.0 A8     35 /EA VPP      2 P1.0 T2    
 14 P3.2 /INT0  25 P2.1 A9     36 P0.7 AD7     3 P1.1 T2EX  
 15 P3.3 /INT1  26 P2.2 A10    37 P0.6 AD6     4 P1.2 ECI   
 16 P3.4 T0     27 P2.3 A11    38 P0.5 AD5     5 P1.3 CEX0  
 17 P3.5 T1     28 P2.4 A12    39 P0.4 AD4     6 P1.4 CEX1  

#
8085
Intel 8085 CPU.

       Ŀ
    X1 1       40 VCC
    X2 2           39 HOLD
RSTOUT 3           38 HLDA
   SOD 4           37 CLK
   SID 5           36 /RSTIN
  TRAP 6           35 RDY
 RST75 7           34 IO//M
 RST65 8           33 S1
 RST55 9           32 /RD
  INTR 10   8085   31 /WR
 /INTA 11          30 ALE
   AD0 12          29 S0
   AD1 13          28 A15
   AD2 14          27 A14
   AD3 15          26 A13
   AD4 16          25 A12
   AD5 17          24 A11
   AD6 18          23 A10
   AD7 19          22 A9
   GND 20          21 A8
       
#
8086
Intel 8086 CPU.

     Ŀ
 GND 1       40 VCC
AD14 2           39 AD15
AD13 3           38 A16  S3
AD12 4           37 A17  S4
AD11 5           36 A18  S5
AD10 6           35 A19  S6
 AD9 7           34 /BHE S7
 AD8 8           33 MN//MX
 AD7 9           32 /RD
 AD6 10          31 /RQ//GT0 HOLD
 AD5 11   8086   30 /RQ//GT1 HLDA
 AD4 12          29 /LOCK    /WR
 AD3 13          28 /S2      M//IO
 AD2 14          27 /S1      DT//R
 AD1 15          26 /S0      /DEN
 AD0 16          25 QS0      ALE
 NMI 17          24 QS1      /INTA
INTR 18          23 /TEST
 CLK 19          22 READY
 GND 20          21 RST
     
#
8243
8048 Port expander.

     Ŀ
P5.0 1       24 VCC
P4.0 2           23 P5.1
P4.1 3           22 P5.2
P4.2 4           21 P5.3
P4.3 5           20 P6.0
 /CS 6           19 P6.1
PROG 7    8243   18 P6.2
P2.3 8           17 P6.3
P2.2 9           16 P7.3
P2.1 10          15 P7.2
P2.0 11          14 P7.1
 GND 12          13 P7.0
     
#
8250, 16450
Asynchronous serial interface controller.

        Ŀ
     D0 1       40 VCC
     D1 2           39 /RI
     D2 3           38 /DCD
     D3 4           37 /DSR
     D4 5           36 /CTS
     D5 6           35 MR
     D6 7           34 /OUT1
     D7 8           33 /DTR
   RCLK 9           32 /RTS
    SIN 10  16450   31 /OUT2
   SOUT 11   8250   30 INTR
    CS0 12          29 CSOUT
    CS1 13          28 A0
   /CS2 14          27 A1
/CLKOUT 15          26 A2
     X1 16          25 /ADS
     X0 17          24
    /WR 18          23 DDIS
     WR 19          22 RD
    GND 20          21 /RD
        
#
8253, 8254
Programmable interval timer/counter.

     Ŀ
  D7 1       24 VCC
  D6 2           23 /WR
  D5 3           22 /RD
  D4 4           21 /CE
  D3 5           20 A1
  D2 6    8253   19 A0
  D1 7    8254   18 CLK2
  D0 8           17 OUT2
CLK0 9           16 G2
OUT0 10          15 CLK1
  G0 11          14 G1
 GND 12          13 OUT1
     
#
8255
Parallel Peripheral Interface.

    Ŀ
PA3 1       40 PA4
PA2 2           39 PA5
PA1 3           38 PA6
PA0 4           37 PA7
/RD 5           36 /WR
/CE 6           35 RST
GND 7           34 D0
 A1 8           33 D1
 A0 9           32 D2
PC7 10   8255   31 D3
PC6 11          30 D4
PC5 12          29 D5
PC4 13          28 D6
PC0 14          27 D7
PC1 15          26 VCC
PC2 16          25 PB7
PC3 17          24 PB6
PB0 18          23 PB5
PB1 19          22 PB4
PB2 20          21 PB3
    
#
8400, Z8400, Z80CPU
Zilog Z80 CPU.

      Ŀ
  A11 1       40 A10
  A12 2           39 A9
  A13 3           38 A8
  A14 4           37 A7
  A15 5           36 A6
  CLK 6           35 A5
   D4 7           34 A4
   D3 8           33 A3
   D5 9           32 A2
   D6 10   Z8400  31 A1
  VCC 11    CPU   30 A0
   D2 12          29 GND
   D7 13          28 /RFSH
   D0 14          27 /M1
   D1 15          26 /RST
 /INT 16          25 /BUSRQ
 /NMI 17          24 /WAIT
/HALT 18          23 /BUSAK
/MREQ 19          22 /WR
/IORQ 20          21 /RD
      
#
8410, Z8410, Z80DMA
Z80 DMA controller.

          Ŀ
       A5 1       40 A6
       A4 2           39 A7
       A3 3           38 IEI
       A2 4           37 /INT /PULSE
       A1 5           36 IEO
       A0 6           35 D0
      CLK 7           34 D1
      /WR 8           33 D2
      /RD 9           32 D3
    /IORQ 10   Z8410  31 D4
      VCC 11    DMA   30 GND
    /MREQ 12          29 D5
     /BAO 13          28 D6
     /BAI 14          27 D7
   /BUSRQ 15          26 /M1
/CE /WAIT 16          25 RDY
      A15 17          24 A8
      A14 18          23 A9
      A13 19          22 A10
      A12 20          21 A11
          
#
8420, Z8420, Z80PIO
Z80 parallel I/O.

       Ŀ
    D2 1       40 D3
    D7 2           39 D4
    D6 3           38 D5
   /CE 4           37 /M1
C/D A1 5           36 /IORQ
B/A A0 6           35 /RD
   PA7 7           34 PB7
   PA6 8           33 PB6
   PA5 9           32 PB5
   PA4 10   Z8420  31 PB4
   GND 11    PIO   30 PB3
   PA3 12          29 PB2
   PA2 13          28 PB1
   PA1 14          27 PB0
   PA0 15          26 VCC
 /ASTB 16          25 CLK
 /BSTB 17          24 IEI
  ARDY 18          23 /INT
    D0 19          22 IEO
    D1 20          21 BRDY
       
#
8430, Z8430
Z80 Counter-Timer Circuit.

        Ŀ
     D4 1       28 D3
     D5 2           27 D2
     D6 3           26 D1
     D7 4           25 D0
    GND 5           24 VCC
    /RD 6           23 CLK0 TRG0
ZC0 TO0 7   Z8430   22 CLK1 TRG1
ZC1 TO1 8    CTC    21 CLK2 TRG2
ZC2 TO2 9           20 CLK3 TRG3
  /IORQ 10          19 A1
    IEO 11          18 A0
   /INT 12          17 /RST
    IEI 13          16 /CE
    /M1 14          15 CLK
        
#
8440, 8470, Z8440, Z80SIO0, Z8470, Z80DART
Z80 dual async/sync serial I/O.
Z8470 has no synchronous capabilities.

        Ŀ
     D1 1       40 D0
     D3 2           39 D2
     D5 3           38 D4
     D7 4           37 D6
   /INT 5           36 /IORQ
    IEI 6           35 /CE
    IEO 7           34 A0 B/A
    /M1 8           33 A1 C/D
    VCC 9           32 /RD
/W_RDYA 10   Z8440  31 GND
 /SYNCA 11   SIO-0  30 /W_RDYB
   RxDA 12          29 /SYNCB
  /RxCA 13          28 RxDB
  /TxCA 14          27 /RxTxCB
   TxDA 15          26 TxDB
  /DTRA 16          25 /DTRB
  /RTSA 17          24 /RTSB
  /CTSA 18          23 /CTSB
  /DCDA 19          22 /DCDB
    CLK 20          21 /RST
        
#
8441, Z8441, Z80SIO1
Z80 dual async/sync serial I/O (bonding option #1).

        Ŀ
     D1 1       40 D0
     D3 2           39 D2
     D5 3           38 D4
     D7 4           37 D6
   /INT 5           36 /IORQ
    IEI 6           35 /CE
    IEO 7           34 A0 B/A
    /M1 8           33 A1 C/D
    VCC 9           32 /RD
/W_RDYA 10   Z8441  31 GND
 /SYNCA 11   SIO-1  30 /W_RDYB
   RxDA 12          29 /SYNCB
  /RxCA 13          28 RxDB
  /TxCA 14          27 /RxCB
   TxDA 15          26 /TxCB
  /DTRA 16          25 TxDB
  /RTSA 17          24 /RTSB
  /CTSA 18          23 /CTSB
  /DCDA 19          22 /DCDB
    CLK 20          21 /RST
        
#
8442, Z8442, Z80SIO2
Z80 dual async/sync serial I/O (bonding option #2).

         Ŀ
      D1 1       40 D0
      D3 2           39 D2
      D5 3           38 D4
      D7 4           37 D6
    /INT 5           36 /IORQ
     IEI 6           35 /CE
     IEO 7           34 A0 B/A
     /M1 8           33 A1 C/D
     VCC 9           32 /RD
 /W_RDYA 10   Z8442  31 GND
  /SYNCA 11   SIO-2  30 /W_RDYB
    RxDA 12          29 RxDB
   /RxCA 13          28 /RxCB
   /TxCA 14          27 /TxCB
    TxDA 15          26 TxDB
   /DTRA 16          25 /DTRB
   /RTSA 17          24 /RTSB
   /CTSA 18          23 /CTSB
   /DCDA 19          22 /DCDB
     CLK 20          21 /RST
         
#
8530, 8531, Z8530, Z8531
Zilog Serial Comminucations Controller.
Z8531 has no synchronous capabilities.

          Ŀ
       D1 1       40 D0
       D3 2           39 D2
       D5 3           38 D4
       D7 4           37 D6
     /INT 5           36 /RD
      IEO 6           35 /WR
      IEI 7           34 A0 A/B
   /INTAK 8           33 /CE
      VCC 9           32 A1 D/C
  /W_REQA 10   Z8530  31 GND
   /SYNCA 11    SCC   30 /W_REQB
   /RTxCA 12          29 /SYNCB
     RxDA 13          28 /RTxCB
   /TRxCA 14          27 RxDB
     TxDA 15          26 /TRxCB
/DTR_REQA 16          25 TxDB
    /RTSA 17          24 /DTR_REQB
    /CTSA 18          23 /RTSB
    /DCDA 19          22 /CTSB
      CLK 20          21 /DCDB
          
#
8570
IC 256x8 static RAM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 GND
 A2 3  8570  6 SCL
GND 4        5 SDA
    
#
8571
IC 128x8 static RAM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 GND
 A2 3  8571  6 SCL
GND 4        5 SDA
    
#
8581, 8572
IC 128x8 EEPROM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2  8572  7 GND
 A2 3  8581  6 SCL
GND 4        5 SDA
    
#
8582
IC 256x8 EEPROM.
Address is 1010xxx where x can be specified by the A0-2 inputs.

    Ŀ
 A0 1    8 VCC
 A1 2        7 GND
 A2 3  8582  6 SCL
GND 4        5 SDA
    
#
8583
IC Clock/Calendar with 240x8 static RAM.
Address is 101000x where x can be specified by the A0 input.

    Ŀ
 X1 1    8 VCC
 X0 2        7 /INT
 A0 3  8583  6 SCL
GND 4        5 SDA
    
#
8592
IC 2x256x8 EEPROM.
Address is 1010xxy where x can be specified by the A1-2 inputs,
and y selects the 256-byte bank to use.
A0 has no function, but must be connected to GND or VCC.

    Ŀ
 A0 1    8 VCC
 A1 2        7 GND
 A2 3  8582  6 SCL
GND 4        5 SDA
    
#
9306
Serial 16x16 EEPROM.

    Ŀ
 CD 1    8 VCC
CLK 2        7
 DI 3  9306  6
 DO 4        5 GND
    
#
9346
Serial 64x16 EEPROM.

    Ŀ
 CD 1    8 VCC
CLK 2        7
 DI 3  9346  6
 DO 4        5 GND
    
#
9356
Serial 256x8/128x16 EEPROM.

    Ŀ
 CD 1    8 VCC
CLK 2        7
 DI 3  9356  6 x16//x8
 DO 4        5 GND
    
#
9366
Serial 512x8/256x16 EEPROM.

    Ŀ
 CD 1    8 VCC
CLK 2        7
 DI 3  9366  6 x16//x8
 DO 4        5 GND
    
#
CNY74-2
Dual optocouplers.

   Ŀ
1A 1    8 1E
1K 2  CNY   7 1C
2K 3  74-2  6 2C
2A 4        5 2E
   
#
CNY74-4
Quad optocouplers.

   Ŀ
1A 1   16 1E
1K 2       15 1C
2K 3       14 2C
2A 4  CNY  13 2E
3A 5  74-4 12 3E
3K 6       11 3C
4K 7       10 4C
4A 8        9 4E
   
#
DS1202
Real-time clock with 3-wire serial interface and 24 bytes RAM.

    Ŀ
    1    8 VCC
 X1 2   DS   7 CLK
 X2 3  1202  6 DQ
GND 4        5 /RST
    
#
DS1210
Nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.

      Ŀ           Ŀ
 VCCo 1    8 VCC       /ENVCC /Y 
VBAT1 2   DS   7 VBAT2     ͵
  TOL 3  1210  6 /Y         1  OK  1 
  GND 4        5 /EN        0  OK  0 
                  X  LO  1 
                             
#
DS1211
1-of-8 inverting decoder/nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.
The Dallas data book suggests this is actually a repackaged DS1212.

      Ŀ           Ŀ
VBAT1 1   20 VCC       /EN S2 S1 S0VCC /Y0/Y1.../Y7/PF
 VCCo 2       19 VBAT2     ͵
  TOL 3       18 /EN        X  X  X  X  LO  1  1  1  1  0 
  /PF 4       17 /Y0        1  0  0  0  OK  0  1  1  1  1 
  /Y7 5   DS  16 /Y1        0  0  0  1  OK  1  0  1  1  1 
  /Y6 6  1211 15 /Y2        0  .  .  .  OK  1  1  .  1  1 
   S2 7       14 /Y3        0  1  1  1  OK  1  1  1  0  1 
   S1 8       13           
   S0 9       12 /Y4
  GND 10      11 /Y5
      
#
DS1212
1-of-16 inverting decoder/nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.

      Ŀ        Ŀ
VBAT1 1       28 VCC    /EN S3 S2 S1 S0VCC /Y0/Y1.../Y15/PF
 VCCo 2           27 VBAT2  ͵
  TOL 3           26 /EN     X  X  X  X  X  LO  1  1  1  1   0 
  /PF 4           25 /Y0     1  0  0  0  0  OK  0  1  1  1   1 
 /Y15 5           24 /Y1     0  0  0  0  1  OK  1  0  1  1   1 
 /Y14 6           23 /Y2     0  .  .  .  .  OK  1  1  .  1   1 
 /Y13 7     DS    22 /Y3     0  1  1  1  1  OK  1  1  1  0   1 
 /Y12 8    1212   21 /Y4    
 /Y11 9           20 /Y5
   S3 10          19 /Y6
   S2 11          18 /Y7
   S1 12          17 /Y8
   S0 13          16 /Y9
  GND 14          15 /Y10
      
#
DS1285, DS1287, DS1287A
Real-time clock with 50 bytes RAM.
DS1287(A) has built-in quartz crystal and lihium battery, and therefore
the X1, X2 and VBAT pins are no-connect.  On the (older) DS1287 the /RCLR
pin is no-connect as well.

    Ŀ
MOT 1       24 VCC
 X1 2           23 SQW
 X2 3           22
AD0 4           21 /RCLR
AD1 5           20 VBAT
AD2 6   DS1285  19 /INT
AD3 7           18 /RST
AD4 8           17 DS
AD5 9           16 GND
AD6 10          15 R//W
AD7 11          14 AS
GND 12          13 /CE
    
#
DS2009, DS2010, DS2011, DS2012, DS2013
512x9 (2009), 1024x9 (2010), 2048x9 (2011), 4096x9 (2012), 8192x9 (2013) FIFO.

      Ŀ
  /WR 1       28 VCC
   D8 2           27 D4
   D3 3           26 D5
   D2 4           25 D6
   D1 5           24 D7
   D0 6           23 /FL /RT
  /XI 7           22 /RST
/FULL 8   DS20xx  21 /EMPTY
   Q0 9           20 /XO /HF
   Q1 10          19 Q7
   Q2 11          18 Q6
   Q3 12          17 Q5
   Q8 13          16 Q4
  GND 14          15 /RD
      
#
LF353
Dual JFET-input operational amplifiers.

     Ŀ
1OUT 1    8 VCC
-1In 2        7 2OUT
+1In 3 LF353  6 -2In
 VEE 4        5 +2In
     
#
LM317T
1.2 to 57V 1,5A positive power supply regulator.

TO 220
Ŀ2
͵
 
    1: Adj
      2: Vout
      3: Vin
1 2 3
#
LM334
Current mode temperature sensor.

TO 92
ķ
 
½    1: Iin
      2: Rset
      3: GND
1 2 3
#
LM337T
-1.2 to -57V 1,5A negative power supply regulator.

TO 220
Ŀ2
͵
 
    1: Adj
      2: Vin
      3: Vout
1 2 3
#
LM338
1.2 to 32V 5A positive power supply regulator.

TO 220
Ŀ2
͵
 
    1: Adj
      2: Vout
      3: Vin
1 2 3
#
LM34
Voltage mode temperature sensor.
Available in Fahrenheit or Celsius models and multiple temperature sense
ranges.  Output is 10mv/degree regardless of VCC (+5 to +30 V).

TO 92
ķ
 
½    1: VCC
      2: Vout
      3: GND
1 2 3
#
LM350
1.2 to 32V 3A positive power supply regulator.

TO 220
Ŀ2
͵
 
    1: Adj
      2: Vout
      3: Vin
1 2 3
#
LM837, LF347
Quad low-noise operational amplifiers.

     Ŀ
1OUT 1   14 4OUT
-1In 2       13 -4In
+1In 3       12 +4In
 VCC 4 LM837 11 VEE
+2In 5       10 +3In
-2In 6        9 -3In
2OUT 7        8 3OUT
     
#
MAX232
5V RS232 transceiver.
To operate, connect two 10 capacitors to the C1 and C2 pins, one between
the V- and GND, and one between V+ and GND.

      Ŀ
  C1+ 1   16 VCC
   V+ 2       15 GND
  C1- 3       14 T1out
  C2+ 4  MAX  13 R1in
  C2- 5  232  12 R1out
   V- 6       11 T1in
T2out 7       10 T2in
 R2in 8        9 R2out
      
#
MAX703
uP supervisor circuit with battery backup.
/RST remains low for 200ms after VCC exceeds 4.65V.  On power failure 
VCCo is connected to VBAT, PFI and /MR are disabled, /RST and /PFO are low.

     Ŀ
VCCo 1    8 VBAT
 VCC 2  MAX   7 /RST 
 GND 3  703   6 /MR
 PFI 4        5 /PFO 
     
#
MC145436
DTMF decoder (Motorola)
DV goes high when a tone is detected on IN (-32..-2dB).
XEN is oscillator enable (pull high, and connect a Xtal // 1M resistor to
X1 and X2).  If XEN is low, ATB can be used to connect multiple chips
together.  GT determines the guard time, 0=short 1=long.

      Ŀ
   D1 1   14 D2
   D0 2       13 D3
   OE 3       12 DV
  VCC 4  MC14 11 ATB
   GT 5  5436 10 X1
  XEN 6        9 X2
   IN 7        8 GND
      
#
MCT9001
Dual optocouplers.

   Ŀ
1A 1    8 1C
1K 2  MCT   7 1E
2A 3  9001  6 2C
2K 4        5 2E
   
#
MOC5010
Linear amplifier optocoupler.

  Ŀ
A 1    6 VCC
K 2  5010  5 GND
  3        4 OUT
  
#
PIC1654, PIC1656 (DIP)
MicroChip PIC microcontrollers.

     Ŀ
 RA2 1   18 RA1
 RA3 2       17 RA0
RTCC 3       16 X1
/RST 4  PIC  15 X0
 GND 5 16C54 14 VCC
 RB0 6 16C56 13 RB7
 RB1 7       12 RB6
 RB2 8       11 RB5
 RB3 9       10 RB4
     

#
PIC1654, PIC1656 (SO)
MicroChip PIC microcontrollers.

     Ŀ
 RA2 1   20 RA1
 RA3 2       19 RA0
RTCC 3       18 X1
/RST 4  PIC  17 X0
 GND 5 16C54 16 VCC
 GND 6 16C55 15 VCC
 RB0 7       14 RB7
 RB1 8       13 RB6
 RB2 9       12 RB5
 RB3 10      11 RB4
     
#
PIC1655, PIC1657 (DIP)
MicroChip PIC microcontrollers.

     Ŀ
RTCC 1   28 /RST
 VCC 2       27 X1
     3       26 X0
 GND 4       25 RC7
     5       24 RC6
 RA0 6  PIC  23 RC5
 RA1 7 16C55 22 RC4
 RA2 8 16C57 21 RC3
 RA3 9       20 RC2
 RB0 10      19 RC1
 RB1 11      18 RC0
 RB2 12      17 RB7
 RB3 13      16 RB6
 RB4 14      15 RB5
     
#
PIC1655, PIC1657 (SO)
MicroChip PIC microcontrollers.

     Ŀ
 GND 1   28 /RST
RTCC 2       27 X1
 VCC 3       26 X0
 VCC 4       25 RC7
 RA0 5       24 RC6
 RA1 6  PIC  23 RC5
 RA2 7 16C55 22 RC4
 RA3 8 16C57 21 RC3
 RB0 9       20 RC2
 RB1 10      19 RC1
 RB2 11      18 RC0
 RB3 12      17 RB7
 RB4 13      16 RB6
 GND 14      15 RB5
     
#
PIC1671, PIC1684
MicroChip PIC microcontrollers.

     Ŀ
 RA2 1   18 RA1
 RA3 2       17 RA0
RTCC 3       16 X1
/RST 4  PIC  15 X0
 GND 5 16C71 14 VCC
 RB0 6 16C84 13 RB7
 RB1 7       12 RB6
 RB2 8       11 RB5
 RB3 9       10 RB4
     
#
SIMM30
8/9-bit 30-pin Single Inline Memory Module.
If present, the ninth (parity) bit has separate data I/O and /CAS signals.
At one time, SIMMs with soldered-on pins (called SIPs) were also available.
Note: A11 is used as a battery connection in the DS2219 nonvolatile DRAM.

         Ŀ
      1     O   
             
  VCC  Ŀ
 /CAS        
   D0  ٳ
   A0  Ŀ
   A1        
   D1  ٳ
   A2  Ŀ
   A3        
  GND  ٳ
   D2  Ŀ
   A4        
   A5  ٳ
   D3  Ŀ
   A6        
   A7  ٳ
   D4  Ŀ
   A8        
   A9  ٳ
  A10  Ŀ
   D5        
  /WR  ٳ
  GND  Ŀ
   D6        
  A11  ٳ
   D7          
   Q8  Ŀ
 /RAS  Parity
/CAS8  ٳ
   D8          
  VCC          
      Ŀ       
      30    O   
         
#
TIL111, TIL112, TIL116, TIL117, TIL118, TIL124, TIL125, TIL126, CNY17, 4N25
Optocoupler.

  Ŀ
A 1    6 B
K 2        5 C
  3        4 E
  
#
TIL113, TIL119
Optocoupler with darlington transistor output configuration.

  Ŀ
A 1    6 B
K 2        5 C
  3        4 E
  
#
TL074
Quad low-noise JFET-input operational amplifiers.

     Ŀ
1OUT 1   14 4OUT
-1In 2       13 -4In
+1In 3       12 +4In
 VCC 4 TL074 11 VEE
+2In 5       10 +3In
-2In 6        9 -3In
2OUT 7        8 3OUT
     
#
TL084
Quad JFET-input operational amplifiers.

     Ŀ
1OUT 1   14 4OUT
-1In 2       13 -4In
+1In 3       12 +4In
 VCC 4 TL084 11 VEE
+2In 5       10 +3In
-2In 6        9 -3In
2OUT 7        8 3OUT
     
#
TL507, TL507C
7-bit PWM output analog-to-digital converter.
Only one of the two power supply pins should be used, 3.5V < VCC < 6V;
8V < VDD < 18V.  At VCC=5V the analog input range is 1.3V < AIN < 3.9V,
or about 25%...75%.  The RST pin can be used to synchronize the output
signal to an external counter; otherwise leave RST tied to VCC.

     Ŀ
  EN 1    8 RST
 CLK 2  TL    7 VDD
 GND 3  507   6 VCC
/OUT 4        5 AIN
     
#
TL783C
1.3 to 125V 700mA high voltage positive power supply regulator.

TO 220
Ŀ2
͵
 
    1: Adj
      2: Vout
      3: Vin
1 2 3
#
TP5088
DTMF encoder (NatSemi).
When /SNGL is low, only the upper or lower tone (selected by GRP) is given.
OUT is open emitter, connect load to GND.

      Ŀ
  VCC 1   14 OUT
   LE 2       13
/SNGL 3       12 D3
  GRP 4  5088 11 D2
  GND 5       10 D1
   X1 6        9 D0
   X0 7        8 MUTE
      
#
UDN2585
7-bit 50V 500mA TTL-input PNP (high-side) darlington driver.
The drivers need no power supply; the GND pin is the common anode of the
seven integrated protection diodes.

    Ŀ             Ŀ
 A0 1   16 /Y0          A /Y 
 A1 2       15 /Y1         ͵
 A2 3       14 /Y2          0  Z 
 A3 4  UDN  13 /Y3          1  0 
 A4 5  2585 12 /Y4         
 A5 6       11 /Y5
 A6 7       10 /Y6
VCC 8        9 GND
    
#
ULN2003, MC1413
7-bit 50V 500mA TTL-input NPN darlington driver.
The drivers need no power supply; the VDD pin is the common cathode of the
seven integrated protection diodes.

    Ŀ             Ŀ
 A0 1   16 /Y0          A /Y 
 A1 2       15 /Y1         ͵
 A2 3       14 /Y2          0  Z 
 A3 4  ULN  13 /Y3          1  0 
 A4 5  2003 12 /Y4         
 A5 6       11 /Y5
 A6 7       10 /Y6
GND 8        9 VDD
    
#
ULN2803
8-bit 50V 500mA TTL-input NPN darlington driver.
The drivers need no power supply; the VDD pin is the common cathode of the
eight integrated protection diodes.

    Ŀ             Ŀ
 A0 1   18 /Y0          A /Y 
 A1 2       17 /Y1         ͵
 A2 3       16 /Y2          0  Z 
 A3 4  ULN  15 /Y3          1  0 
 A4 5  2803 14 /Y4         
 A5 6       13 /Y5
 A6 7       12 /Y6
 A7 8       11 /Y7
GND 9       10 VDD
    



 


Home  |  Online Store  |  Repair Logs  |  Manuals and Schematics  |  Monitor Manuals  |  Component Markings  |  Links

All Content Copyright © 2000-2017 by MikesArcade.com